參數(shù)資料
型號: P89LPC930FDH
廠商: NXP Semiconductors N.V.
元件分類: 8位微控制器
英文描述: 8-bit microcontrollers with two-clock 80C51 core 4 kB-8 kB 3 V Flash with 256-byte data RAM
封裝: P89LPC930FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html<1<week 47, 2004,;P89LPC931FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html&l
文件頁數(shù): 43/55頁
文件大?。?/td> 267K
代理商: P89LPC930FDH
Philips Semiconductors
P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 05 — 15 December 2004
48 of 55
9397 750 14472
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
Parameters are valid over operating temperature range unless otherwise specied. Parts are tested to 2 MHz, but are guaranteed to
operate down to 0 Hz.
[2]
When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until VDD has reached its specied level. When system power is removed VDD will fall below the
minimum specied operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout
detect circuit may be required to hold the device in reset when VDD falls below the minimum specied operating voltage.
tSPIF
Fall time
see Figures
SPI outputs (SPICLK, MOSI,
MISO)
-
100
-
100
ns
SPI inputs (SPICLK, MOSI,
MISO, SS)
-
2000
-
2000
ns
Table 9:
AC characteristics…continued
VDD = 3.0 V to 3.6 V, unless otherwise specied.
Tamb = 40 °Cto+85 °C for industrial, unless otherwise specied.[1]
Symbol
Parameter
Conditions
Variable clock
fosc =18MHz
Unit
Min
Max
Min
Max
Fig 15. SPI master timing (CPHA = 0).
tCLCL
tSPICLKH
tSPICLKL
Master LSB/MSB out
Master MSB/LSB out
tSPIDH
tSPIDSU
tSPICLKL
tSPICLKH
tSPIF
tSPIOH
tSPIDV
tSPIR
tSPIDV
tSPIF
tSPIR
SS
SPICLK
(CPOL = 0)
(output)
002aaa156
SPICLK
(CPOL = 1)
(output)
MISO
(input)
MOSI
(output)
LSB/MSB in
MSB/LSB in
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