參數(shù)資料
型號: P89LPC9161FDH,129
廠商: NXP Semiconductors
文件頁數(shù): 12/27頁
文件大小: 0K
描述: IC 80C51 MCU FLASH 2KB 16TSSOP
標準包裝: 96
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 14
程序存儲器容量: 2KB(2K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b; D/A 1x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
包裝: 管件
其它名稱: 935290261129
2010 Microchip Technology Inc.
Preliminary
DS39979A-page 77
PIC18F87J72 FAMILY
7.0
FLASH PROGRAM MEMORY
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 64 bytes at a time or two bytes at a time. Pro-
gram memory is erased in blocks of 1,024 bytes at a
time. A bulk erase operation may not be issued from
user code.
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
7.1
Table Reads and Table Writes
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:
Table Read (TBLRD)
Table Write (TBLWT)
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Table read operations retrieve data from program
memory and place it into the data RAM space.
Figure 7-1 shows the operation of a table read with
program memory and data RAM.
Table write operations store data from the data memory
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 7.5 “Writing
operation of a table write with program memory and data
RAM.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word-aligned. Therefore, a table block can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word-aligned.
FIGURE 7-1:
TABLE READ OPERATION
Table Pointer(1)
Table Latch (8-bit)
Program Memory
TBLPTRH
TBLPTRL
TABLAT
TBLPTRU
Instruction: TBLRD*
Note 1:
Table Pointer register points to a byte in program memory.
Program Memory
(TBLPTR)
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