參數(shù)資料
型號: P89LPC915HDH
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V Flash with 8-bit A/D converter
中文描述: 8-BIT, FLASH, 18 MHz, MICROCONTROLLER, PDSO14
封裝: PLASTIC,MO-153, SOT402-1, TSSOP-14
文件頁數(shù): 62/72頁
文件大?。?/td> 344K
代理商: P89LPC915HDH
Philips Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data
Rev. 04 — 17 December 2004
62 of 72
9397 750 14397
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table 15:
V
DD
= 3.0 V to 3.6 V unless otherwise specified.
T
amb
=
40
°
C to +85
°
C for industrial,
40
°
C to +125
°
C extended, unless otherwise specified.
[1]
Symbol
Parameter
AC characteristics
Conditions
Variable clock
Min
7.189
7.004
f
osc
= 18 MHz
Min
7.189
7.004
Unit
Max
7.557
7.741
Max
7.557
7.741
f
RCOSC
internal RC oscillator frequency
(nominal f = 7.3728 MHz) trimmed
to
±
1 % at T
amb
= 25
°
C
internal Watchdog oscillator
frequency (nominal f = 400 kHz)
External clock input
f
osc
oscillator frequency
t
CLCL
clock cycle
f
CLKP
CLKLP active frequency
t
CHCX
high time
t
CLCX
low time
t
CLCH
rise time
t
CHCL
fall time
Glitch filter
glitch rejection, P1.5/RST pin
signal acceptance, P1.5/RST pin
glitch rejection, any pin except
P1.5/RST
signal acceptance, any pin except
P1.5/RST
Shift register (UART mode 0)
t
XLXL
serial port clock cycle time
t
QVXH
output data set-up to clock rising
edge
t
XHQX
output data hold after clock rising
edge
t
XHDX
input data hold after clock rising
edge
t
DVXH
input data valid to clock rising edge see
Figure 26
SPI interface
f
SPI
Operating frequency
3.0 MHz (Slave)
4.5 MHz (Master)
t
SPICYC
Cycle time
industrial
extended
MHz
MHz
f
WDOSC
320
520
320
520
kHz
[1]
0
18
-
8
t
CLCL
t
CLCX
t
CLCL
t
CHCX
5
5
-
-
-
22
22
-
-
-
-
-
-
-
5
5
MHz
ns
MHz
ns
ns
ns
ns
see
Figure 27
55
0
22
22
-
-
see
Figure 27
see
Figure 27
see
Figure 27
see
Figure 27
-
125
-
50
-
15
-
125
-
50
-
15
ns
ns
ns
50
-
50
-
ns
see
Figure 26
see
Figure 26
16t
CLCL
13t
CLCL
-
-
888
722
-
-
ns
ns
see
Figure 26
-
t
CLCL
+ 20
-
103
ns
see
Figure 26
-
0
-
0
ns
150
-
150
-
ns
0
-
CCLK
6
CCLK
4
0
-
3
4.5
MHz
MHz
see
Figure 22
,
23
,
24
,
25
3.0 MHz (Slave)
4.5 MHz (Master)
6
CCLK
4
CCLK
-
-
333
222
-
-
ns
ns
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