參數(shù)資料
型號: P89LPC9107FDH
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter
中文描述: 8-BIT, FLASH, 18 MHz, MICROCONTROLLER, PDSO14
封裝: 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP-14
文件頁數(shù): 17/58頁
文件大?。?/td> 257K
代理商: P89LPC9107FDH
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P89LPC9102 special function registers
…continued
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
MSB
9
P
R
1
P
P
8
[1]
Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset values shown for these bits are logic 0s although they are unknown when read.
[2]
All ports are in input-only (high-impedance) state after power-up.
[3]
The RSTSRC register reflects the cause of the P89LPC9102/9103/9107 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset
value is xx110000.
[4]
The only reset source that affects these SFRs is power-on reset.
[5]
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[6]
After reset, the value is 111001x1, i.e., PRE2 to PRE0 are all logic 1s, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog timer reset and is logic 0 after power-on
reset. Other resets will not affect WDTOF.
RSTSRC
RTCCON
Reset source register
Real-time clock control
DFh
D1h
-
-
BOF
RTCS0
POF
-
-
-
R_WD
-
R_SF
ERTC
R_EX
RTCEN
[3]
RTCF
RTCS1
60
[2]
[4]
011xxx00
RTCH
RTCL
SP
TAMOD
Real-time clock register high
Real-time clock register low
Stack pointer
Timer 0 and 1 auxiliary mode
D2h
D3h
81h
8Fh
00
[4]
00
[4]
07
00
00000000
00000000
00000111
xxx0xxx0
-
-
-
T1M2
8C
TR0
-
-
-
T0M2
88
-
Bit address
8F
TF1
8E
TR1
8D
TF0
8B
-
8A
-
89
-
TCON*
TH0
TH1
TL0
TL1
TMOD
TRIM
WDCON
WDL
WFEED1
WFEED2
Timer 0 and 1 control
Timer 0 high
Timer 1 high
Timer 0 low
Timer 1 low
Timer 0 and 1 mode
Internal oscillator trim register
Watchdog control register
Watchdog load
Watchdog feed 1
Watchdog feed 2
88h
8Ch
8Dh
8Ah
8Bh
89h
96h
A7h
C1h
C2h
C3h
00
00
00
00
00
00
00000000
00000000
00000000
00000000
00000000
00000000
-
-
T1M1
TRIM.5
PRE0
T1M0
TRIM.4
-
-
-
T0M1
TRIM.1
WDTOF
T0M0
TRIM.0
WDCLK
RCCLK
PRE2
ENCLK
PRE1
TRIM.3
-
TRIM.2
WDRUN
[5] [4]
[6] [4]
FF
11111111
Table 7:
Bit functions and addresses
Reset value
Hex
LSB
Binary
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