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參數(shù)資料
| 型號： | P89LPC9102FTK |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter |
| 中文描述： | 8-BIT, FLASH, 18 MHz, MICROCONTROLLER, PDSO10 |
| 封裝： | 3 X 3 MM, 0.85 MM HEIGHT, PLASTIC, MO-229, SOT-650-1, HVSON-10 |
| 文件頁數(shù)： | 28/58頁 |
| 文件大?。?/td> | 257K |
| 代理商： | P89LPC9102FTK |
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9397 750 14655
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 April 2005
28 of 58
Philips Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
frequency above 12 MHz, in some applications, an external brownout detect circuit
may be required to hold the device in reset when V
DD
falls below the minimum
specified operating voltage.
8.7 CCLK wake-up delay
The P89LPC9102/9103/9107 has an internal wake-up timer that delays the clock until it
stabilizes depending to the clock source used.
8.8 CCLK modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing
register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
retain the ability to respond to events that would not exit Idle mode by executing its normal
program at a lower rate. This can also allow bypassing the oscillator start-up time in cases
where Power-down mode would otherwise be used. The value of DIVM may be changed
by the program at any time without interrupting code execution.
8.9 Low power select
If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower
the power consumption further. On any reset, CLKLP is logic 0.
8.10 Memory organization
The various P89LPC9102/9103/9107 memory spaces are as follows:
DATA
128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect
addressing, using instruction other than MOVX and MOVC. All or part of the stack
may be in this area.
SFR
Special Function Registers. Selected CPU registers and peripheral control and status
registers, accessible only via direct addressing.
CODE
1 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction.
8.11 Interrupts
The P89LPC9102 supports nine interrupt sources: timers 0 and 1, brownout detect,
watchdog timer/RTC, keyboard, comparator 1, and the A/D converter.
The P89LPC9103/9107 support nine interrupt sources: timers 0 and 1, serial port Tx,
serial port Rx, combined serial port Rx/Tx, brownout detect, watchdog timer/RTC,
keyboard, comparator, and the A/D converter.
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in
the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global
disable bit, EA, which disables all interrupts.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| P89LPC9102FTK,115 | 功能描述:8位微控制器 -MCU PREF PART P89LPC9103FTK-G RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P89LPC9102FTK-G | 功能描述:8位微控制器 -MCU 80C51 1K FL 128B RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P89LPC9103 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable flash with 8-bit A/D converter |
| P89LPC9103FTK | 制造商:NXP Semiconductors 功能描述:MCU 8BIT 80C51 1K FLASH HVSON-10 制造商:NXP Semiconductors 功能描述:MCU 8BIT 80C51 1K FLASH, HVSON-10 |
| P89LPC9103FTK,115 | 功能描述:8位微控制器 -MCU 80C51 1K FL 128B RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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