參數(shù)資料
型號: P89LPC9102
廠商: NXP Semiconductors N.V.
元件分類: 8位微控制器
英文描述: 8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter
中文描述: 8位微控制器兩個小時加速80C51的核心具有1KB 3伏字節(jié)可擦除閃存的8位A / D轉(zhuǎn)換器
文件頁數(shù): 35/58頁
文件大小: 257K
代理商: P89LPC9102
9397 750 14655
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 April 2005
35 of 58
Philips Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
8.16.6
Timer overflow toggle output (P89LPC9102/9107)
Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer
overflow occurs. The same device pins that are used for the T0 and T1 count inputs are
also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first
timer overflow when this mode is turned on.
8.17 RTC/system timer
The P89LPC9102/9103/9107 has a simple RTC that allows a user to continue running an
accurate timer while the rest of the device is powered-down. The RTC can be a wake-up
or an interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler
and a 16-bit loadable down counter. When it reaches all logic 0s, the counter will be
reloaded again and the RTCF flag will be set. The clock source for this counter is the
CCLK. Only power-on reset will reset the RTC and its associated SFRs to the default
state.
8.18 UART (P89LPC9103/9107)
The P89LPC9103/9107 has an enhanced UART that is compatible with the conventional
80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The
P89LPC9103/9107 does include an independent Baud Rate Generator. The baud rate
can be selected from CCLK (divided by a constant), Timer 1 overflow, or the independent
Baud Rate Generator. In addition to the baud rate generation, enhancements over the
standard 80C51 UART include Framing Error detection, automatic address recognition,
selectable double buffering and several interrupt options. The UART can be operated in
four modes: shift register, 8-bit UART, 9-bit UART, and
CCLK
32
or
CCLK
16
.
8.18.1
Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. Eight bits are
transmitted or received, LSB first. The baud rate is fixed at
1
16
of the CPU clock
frequency.
8.18.2
Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0),
8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored
in RB8 in Special Function Register SCON. The baud rate is variable and is determined
by the Timer 1 overflow rate or the Baud Rate Generator (described in
Section 8.18.5
“Baud rate generator and selection”
).
8.18.3
Mode 2
11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data
bits (LSB first), a programmable 9
th
data bit, and a stop bit (logic 1). When data is
transmitted, the 9
th
data bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1.
Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is
received, the 9
th
data bit goes into RB8 in Special Function Register SCON, while the stop
bit is not saved. The baud rate is programmable to either
1
16
or
1
32
of the CPU clock
frequency, as determined by the SMOD1 bit in PCON.
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