參數(shù)資料
型號(hào)： P89C739ABA
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-bit Flash microcontrollers
中文描述： 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 28/64頁(yè)
文件大小： 360K
代理商： P89C739ABA
1998 Apr 07
28
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
13 REDUCED POWER MODES
Two software selectable modes of reduced power
consumption are implemented: Idle and Power-down
mode.
Idle mode operation permits the interrupt, serial ports and
timer blocks to function while the CPU is halted. The
following functions remain active during Idle mode:
Timer 0, Timer 1, Timer 2, Watchdog Timer
UART
External interrupt.
These functions may generate an interrupt or reset and
thus end the Idle mode.
The Power-down mode operation freezes the oscillator.
and can only be activated by setting the PD bit in the SFR
PCON (see Fig.17).
13.1
Idle mode
The instruction that sets IDL (PCON.0) is the last
instruction executed in the normal operating mode before
Idle mode is activated. Once in the Idle mode, the CPU
status is preserved in its entirety: the Stack Pointer,
Program Counter, Program Status Word, Accumulator,
RAM and all other registers maintain their data during Idle
mode. The status of external pins during Idle mode is
shown in Table 20.
There are three ways to terminate the Idle mode:
Activation of any enabled interrupt will cause IDL
(PCON.0) to be cleared by hardware terminating Idle
mode. The interrupt is serviced, and following return
from interrupt instruction RETI, the next instruction to be
executed will be the one which follows the instruction
that wrote a logic 1 to PCON.0.
The flag bits GF0 (PCON.2) and GF1 (PCON.3) may be
used to determine whether the interrupt was received
during normal execution or during the Idle mode.
For example, the instruction that writes to PCON.0 can
also set or clear one or both flag bits. When Idle mode is
terminated by an interrupt, the service routine can
examine the status of the flag bits.
The second way of terminating the Idle mode is with an
external hardware reset. Since the oscillator is still
running, the hardware reset is required to be active for
two machine cycles (24 oscillator periods) to complete
the reset operation.
The third way of terminating the Idle mode is by internal
watchdog reset.
13.2
Power-down mode
The instruction that sets PD (PCON.1) is the last executed
prior to going into the Power-down mode. The oscillator is
stopped. Note that the Power-down mode also can be
entered when the watchdog has been disabled.
The Power-down mode can be terminated by an external
reset in the same way as in the 80C51 or in addition by any
one of the two external interrupts, IE0 or IE1
(see Section 9.1).
The status of the external pins during Power-down mode
is shown in Table 20. If the Power-down mode is activated
while in external program memory, the port data that is
held in the SFR P2 is restored to Port 2. If the data is a
logic 1, the port pin is held HIGH during the Power-down
mode by the strong pull-up transistor ‘p1’ (see Fig.15).
13.3
Wake-up from Power-down mode
The Power-down mode of the P89C738 can also be
terminated by any one of the two external interrupts, IE0 or
IE1. A termination with an external interrupt does not affect
the internal data memory and does not affect the Special
Function Registers (SFRs). This gives the possibility to
exit Power-down without changing the port output levels.
To terminate the Power-down mode with an external
interrupt, IE0 or IE1 must be switched to be level-sensitive
and must be enabled. The external interrupt input signal
INT0 and INT1 must be kept LOW until the oscillator has
restarted and stabilized (see Fig.16).
In order to prevent any interrupt priority problems during
wake-up, the priority of the desired wake-up interrupt
should be higher than the priorities of all other enabled
interrupt sources. The instruction following the one that put
the device into the Power-down mode will be the first one
which will be executed after an interrupt has been
serviced.
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