參數(shù)資料
型號: P89C668HFA
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 80C51 8-bit Flash microcontroller family 64KB ISP FLASH with 8KB RAM
中文描述: 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, MS-018, SOT-187-2, LCC-44
文件頁數(shù): 19/54頁
文件大小: 299K
代理商: P89C668HFA
Philips Semiconductors
Preliminary data
P89C668
80C51 8-bit Flash microcontroller family
64KB ISP Flash with 8KB RAM
2001 Jul 27
19
Interrupt Priority Structure
The P89C668 has an 8 source four-level interrupt structure (see
Table 8).
There are 4 SFRs associated with the four-level interrupt. They are
the IE, IEN1, IP, and IPH. (See Figures 10, 11, 12, and 13.) The IPH
(Interrupt Priority High) register makes the four-level interrupt
structure possible. The IPH is located at SFR address B7H. The
structure of the IPH register and a description of its bits is shown in
Figure 12.
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
PRIORITY BITS
INTERRUPT PRIORITY LEVEL
IPH.x
IP.x
0
0
Level 0 (lowest priority)
0
1
Level 1
1
0
Level 2
1
1
Level 3 (highest priority)
The priority scheme for servicing the interrupts is the same as that
for the 80C51, except there are four interrupt levels rather than two
as on the 80C51. An interrupt will be serviced as long as an interrupt
of equal or higher priority is not already being serviced. If an
interrupt of equal or higher level priority is being serviced, the new
interrupt will wait until it is finished before being serviced. If a lower
priority level interrupt is being serviced, it will be stopped and the
new interrupt serviced. When the new interrupt is finished, the lower
priority level interrupt that was stopped will be completed.
Table 8.
Interrupt Table
SOURCE
POLLING PRIORITY
REQUEST BITS
HARDWARE CLEAR
N (L)
1
VECTOR ADDRESS
X0
1
IE0
Y (T)
2
03H
SI01 (I
2
C)
2
N
2BH
T0
3
TP0
Y
0BH
X1
4
IE1
N (L)
Y (T)
13H
T1
5
TF1
Y
1BH
SP
6
RI, TI
N
23H
T2
7
TF2, EXF2
N
3BH
PCA
8
CF, CCFn
n = 0–4
N
33H
NOTES:
1. L = Level activated
2. T = Transition activated
EX0
IEN0 (0A8H)
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
BIT
IEN0.7
SYMBOL
EA
FUNCTION
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
PCA interrupt enable bit
I
2
C interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
IEN0.6
IEN0.5
IEN0.4
IEN0.3
IEN0.2
IEN0.1
IEN0.0
EC
ES1
ES0
ET1
EX1
ET0
EX0
SU01460
ET0
EX1
ET1
ES0
ES1
EC
EA
0
1
2
3
4
5
6
7
Figure 10. IE Registers
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