參數(shù)資料
型號(hào)： P89C54X2FA
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： 80C51 8-bit Flash microcontroller family
中文描述： 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 17/32頁(yè)
文件大?。?/td> 212K
代理商： P89C54X2FA
Philips Semiconductors
Product specification
89C51/89C52/89C54/89C58
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
1999 Oct 27
17
Interrupt Priority Structure
The 89C51/89C52/89C54/89C58 have a 6-source four-level
interrupt structure.
There are 3 SFRs associated with the four-level interrupt. They are
the IE, IP, and IPH. (See Figures 10, 11, and 12.) The IPH (Interrupt
Priority High) register makes the four-level interrupt structure
possible. The IPH is located at SFR address B7H. The structure of
the IPH register and a description of its bits is shown in Figure 12.
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
PRIORITY BITS
INTERRUPT PRIORITY LEVEL
IPH.x
IP.x
0
0
Level 0 (lowest priority)
0
1
Level 1
1
0
Level 2
1
1
Level 3 (highest priority)
There are four interrupt levels rather than two as on the 80C51. An
interrupt will be serviced as long as an interrupt of equal or higher
priority is not already being serviced. If an interrupt of equal or
higher level priority is being serviced, the new interrupt will wait until
it is finished before being serviced. If a lower priority level interrupt is
being serviced, it will be stopped and the new interrupt serviced.
When the new interrupt is finished, the lower priority level interrupt
that was stopped will be completed.
Table 7.
Interrupt Table
SOURCE
POLLING PRIORITY
REQUEST BITS
HARDWARE CLEAR
N (L)
1
VECTOR ADDRESS
X0
1
IE0
Y (T)
2
03H
T0
2
TP0
Y
0BH
X1
3
IE1
N (L)
Y (T)
13H
T1
4
TF1
Y
1BH
SP
5
RI, TI
N
23H
T2
6
TF2, EXF2
N
2BH
NOTES:
1. L = Level activated
2. T = Transition activated
EX0
IE (0A8H)
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
BIT
IE.7
SYMBOL
EA
FUNCTION
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
Not implemented. Reserved for future use.
Timer 2 interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
—
ET2
ES
ET1
EX1
ET0
EX0
SU00571
ET0
EX1
ET1
ES
ET2
—
EA
0
1
2
3
4
5
6
7
Figure 10. IE Registers
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參數(shù)描述
P89C54X2FA/00,529 功能描述:IC 80C51 MCU 256 RAM 44PLCC RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:89C 標(biāo)準(zhǔn)包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設(shè)備:POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):21 程序存儲(chǔ)器容量:40KB（20K x 16） 程序存儲(chǔ)器類(lèi)型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 6x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤(pán) 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323
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P89C557E4EFB/01,557 制造商:NXP Semiconductors 功能描述:
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