參數(shù)資料
型號(hào)： P89C51UBBB
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash
中文描述： 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP44
封裝： PLASTIC, QFP-44
文件頁(yè)數(shù)： 33/68頁(yè)
文件大小： 404K
代理商： P89C51UBBB
Philips Semiconductors
Preliminary data
P89C51RA2/RB2/RC2/RD2xx
80C51 8-bit Flash microcontroller family
8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM
2002 Jul 18
33
Reduced EMI Mode
The AO bit (AUXR.0) in the AUXR register when set disables the
ALE output unless the CPU needs to perform an off-chip memory
access.
Reduced EMI Mode
AUXR (8EH)
7
6
5
4
3
2
1
0
–
–
–
–
–
–
EXTRAM
AO
AUXR.1
AUXR.0
EXTRAM
AO
See more detailed description in Figure 38.
Dual DPTR
The dual DPTR structure (see Figure 24) is a way by which the chip
will specify the address of an external data memory location. There
are two 16-bit DPTR registers that address the external memory,
and a single bit called DPS = AUXR1/bit0 that allows the program
code to switch between them.
New Register Name: AUXR1#
SFR Address: A2H
Reset Value: xxxxxxx0B
AUXR1 (A2H)
7
6
5
4
3
2
1
0
–
–
ENBOOT
–
GF2
0
–
DPS
Where:
DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.
Select Reg
DPS
DPTR0
DPTR1
0
1
The DPS bit status should be saved by software when switching
between DPTR0 and DPTR1.
The GF2 bit is a general purpose user-defined flag. Note that bit 2 is
not writable and is always read as a zero. This allows the DPS bit to
be quickly toggled simply by executing an INC AUXR1 instruction
without affecting the GF2 bit.
The ENBOOT bit determines whether the BOOTROM is enabled
or disabled.
This bit will automatically be set if the status byte is
non zero during reset or PSEN is pulled low, ALE floats high, and
EA > V
IH
on the falling edge of reset. Otherwise, this bit will be
cleared during reset.
DPS
DPTR1
DPTR0
DPH
(83H)
DPL
(82H)
EXTERNAL
DATA
MEMORY
SU00745A
BIT0
AUXR1
Figure 24.
DPTR Instructions
The instructions that refer to DPTR refer to the data pointer that is
currently selected using the AUXR1/bit 0 register. The six
instructions that use the DPTR are as follows:
INC DPTR
Increments the data pointer by 1
MOV DPTR, #data16
Loads the DPTR with a 16-bit constant
MOV A, @ A+DPTR
Move code byte relative to DPTR to ACC
MOVX A, @ DPTR
Move external RAM (16-bit address) to
ACC
MOVX @ DPTR , A
Move ACC to external RAM (16-bit
address)
JMP @ A + DPTR
Jump indirect relative to DPTR
The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See Application Note AN458for more details.
相關(guān)PDF資料
PDF描述
P89C51RC2 80C51 8-bit Flash microcontroller family
P89C51RC2HFBD 80C51 8-bit Flash microcontroller family
P89C51RD2HBP 80C51 8-bit Flash microcontroller family
P89C51RD2HXX 80C51 8-bit Flash microcontroller family
P89C51UBAA 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
P89C51UBBB-S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
P89C51UBBB-T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
P89C51UBPN 制造商:NXP Semiconductors 功能描述:
P89C51UFAA 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 4K/8K/16K/32K Flash
P89C51UFAA-T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
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