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參數(shù)資料
| 型號： | P89C51RD2BB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
| 中文描述： | 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 X 1.75 MM, PLASTIC, SOT-307-2, QFP-44 |
| 文件頁數(shù)： | 19/52頁 |
| 文件大小： | 289K |
| 代理商： | P89C51RD2BB |
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Philips Semiconductors
Preliminary specification
89C51RB2/89C51RC2/
89C51RD2
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
1999 Sep 23
19
Interrupt Priority Structure
The 89C51RB2/RC2/RD2 has an 8 source four-level interrupt
structure (see Table 7).
There are 3 SFRs associated with the four-level interrupt. They are
the IE, IP, and IPH. (See Figures 10, 11, and 12.) The IPH (Interrupt
Priority High) register makes the four-level interrupt structure
possible. The IPH is located at SFR address B7H. The structure of
the IPH register and a description of its bits is shown in Figure 12.
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
PRIORITY BITS
INTERRUPT PRIORITY LEVEL
IPH.x
IP.x
0
0
Level 0 (lowest priority)
0
1
Level 1
1
0
Level 2
1
1
Level 3 (highest priority)
The priority scheme for servicing the interrupts is the same as that
for the 80C51, except there are four interrupt levels rather than two
as on the 80C51. An interrupt will be serviced as long as an interrupt
of equal or higher priority is not already being serviced. If an
interrupt of equal or higher level priority is being serviced, the new
interrupt will wait until it is finished before being serviced. If a lower
priority level interrupt is being serviced, it will be stopped and the
new interrupt serviced. When the new interrupt is finished, the lower
priority level interrupt that was stopped will be completed.
Table 7.
Interrupt Table
SOURCE
POLLING PRIORITY
REQUEST BITS
HARDWARE CLEAR
N (L)
1
VECTOR ADDRESS
X0
1
IE0
Y (T)
2
03H
T0
2
TP0
Y
0BH
X1
3
IE1
N (L)
Y (T)
13H
T1
4
TF1
Y
1BH
PCA
5
CF, CCFn
n = 0–4
N
33H
SP
6
RI, TI
N
23H
T2
7
TF2, EXF2
N
2BH
NOTES:
1. L = Level activated
2. T = Transition activated
EX0
IE (0A8H)
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
BIT
IE.7
SYMBOL
EA
FUNCTION
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
PCA interrupt enable bit
Timer 2 interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
EC
ET2
ES
ET1
EX1
ET0
EX0
SU01290
ET0
EX1
ET1
ES
ET2
EC
EA
0
1
2
3
4
5
6
7
Figure 10. IE Registers
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| P89C51RD2BBD/01 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit Flash microcontroller family |
| P89C51RD2BBD/01,55 | 功能描述:IC 80C51 MCU FLASH 64K 44-LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:89C 產(chǎn)品培訓模塊:MCU Product Line Introduction XMEGA Introduction AVR XMEGA USB Connectivity 標準包裝:90 系列:AVR® XMEGA 核心處理器:AVR 芯體尺寸:8/16-位 速度:32MHz 連通性:I²C，IrDA，SPI，UART/USART 外圍設備:欠壓檢測/復位，DMA，POR，PWM，WDT 輸入/輸出數(shù):50 程序存儲器容量:192KB（96K x 16） 程序存儲器類型:閃存 EEPROM 大小:4K x 8 RAM 容量:16K x 8 電壓 - 電源 (Vcc/Vdd):1.6 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 16x12b; D/A 2x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:64-TQFP 包裝:托盤 配用:ATSTK600-RC14-ND - STK600 SOCKET/ADAPTER 64TQFPATSTK600-TQFP64-ND - STK600 SOCKET/ADAPTER 64-TQFPATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMRATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM |
| P89C51RD2BN/01 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit Flash microcontroller family |
| P89C51RD2BN/01,112 | 制造商:NXP Semiconductors 功能描述: |
| P89C51RD2BP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
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