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參數(shù)資料
| 型號(hào)： | P89C51RD2 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 80C51 8-bit Flash microcontroller family |
| 中文描述： | 80C51的8位閃存微控制器系列 |
| 文件頁數(shù)： | 31/68頁 |
| 文件大小： | 404K |
| 代理商： | P89C51RD2 |
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Philips Semiconductors
Preliminary data
P89C51RA2/RB2/RC2/RD2xx
80C51 8-bit Flash microcontroller family
8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM
2002 Jul 18
31
Interrupt Priority Structure
The P89C51RA2/RB2/RC2/RD2xx has a 7 source four-level
interrupt structure (see Table 7).
There are 3 SFRs associated with the four-level interrupt. They are
the IE, IP, and IPH. (See Figures 21, 22, and 23.) The IPH (Interrupt
Priority High) register makes the four-level interrupt structure
possible. The IPH is located at SFR address B7H. The structure of
the IPH register and a description of its bits is shown in Figure 23.
The function of the IPH SFR, when combined with the IP SFR,
determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
PRIORITY BITS
INTERRUPT PRIORITY LEVEL
IPH.x
IP.x
0
0
Level 0 (lowest priority)
0
1
Level 1
1
0
Level 2
1
1
Level 3 (highest priority)
The priority scheme for servicing the interrupts is the same as that
for the 80C51, except there are four interrupt levels rather than two
as on the 80C51. An interrupt will be serviced as long as an interrupt
of equal or higher priority is not already being serviced. If an
interrupt of equal or higher level priority is being serviced, the new
interrupt will wait until it is finished before being serviced. If a lower
priority level interrupt is being serviced, it will be stopped and the
new interrupt serviced. When the new interrupt is finished, the lower
priority level interrupt that was stopped will be completed.
Table 7.
Interrupt Table
SOURCE
POLLING PRIORITY
REQUEST BITS
HARDWARE CLEAR
N (L)
1
VECTOR ADDRESS
X0
1
IE0
Y (T)
2
03H
T0
2
TP0
Y
0BH
X1
3
IE1
N (L)
Y (T)
13H
T1
4
TF1
Y
1BH
PCA
5
CF, CCFn
n = 0–4
N
33H
SP
6
RI, TI
N
23H
T2
7
TF2, EXF2
N
2BH
NOTES:
1. L = Level activated
2. T = Transition activated
EX0
IE (0A8H)
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
BIT
IE.7
SYMBOL
EA
FUNCTION
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
PCA interrupt enable bit
Timer 2 interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
EC
ET2
ES
ET1
EX1
ET0
EX0
SU01290
ET0
EX1
ET1
ES
ET2
EC
EA
0
1
2
3
4
5
6
7
Figure 21. IE Registers
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