參數(shù)資料
型號(hào)： P89C51RC2HFBD
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： 80C51 8-bit Flash microcontroller family
中文描述： 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP44
封裝： 10 X 10 X 1.40 MM, PLASTIC, LQFP-44
文件頁(yè)數(shù)： 43/68頁(yè)
文件大小： 404K
代理商： P89C51RC2HFBD
Philips Semiconductors
Preliminary data
P89C51RA2/RB2/RC2/RD2xx
80C51 8-bit Flash microcontroller family
8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM
2002 Jul 18
43
ERAM
256 or 768 BYTES
UPPER
128 BYTES
INTERNAL RAM
LOWER
128 BYTES
INTERNAL RAM
SPECIAL
FUNCTION
REGISTER
100
FF
00
FF
00
80
80
EXTERNAL
DATA
MEMORY
FFFF
0000
SU01293
Figure 39. Internal and External Data Memory Address Space with EXTRAM = 0
HARDWARE WATCHDOG TIMER (ONE-TIME
ENABLED WITH RESET-OUT FOR
P89C51RA2/RB2/RC2/RD2xx)
The WDT is intended as a recovery method in situations where the
CPU may be subjected to software upset. The WDT consists of a
14-bit counter and the WatchDog Timer reset (WDTRST) SFR. The
WDT is disabled at reset. To enable the WDT, the user must write
01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H.
When the WDT is enabled, it will increment every machine cycle
while the oscillator is running and there is no way to disable the
WDT except through reset (either hardware reset or WDT overflow
reset). When the WDT overflows, it will drive an output reset HIGH
pulse at the RST-pin (see the note below).
Using the WDT
To enable the WDT, the user must write 01EH and 0E1H in sequence
to the WDTRST, SFR location 0A6H. When the WDT is enabled, the
user needs to service it by writing 01EH and 0E1H to WDTRST to
avoid a WDT overflow. The 14-bit counter overflows when it reaches
16383 (3FFFH) and this will reset the device. When the WDT is
enabled, it will increment every machine cycle while the oscillator is
running. This means the user must reset the WDT at least every
16383 machine cycles. To reset the WDT, the user must write 01EH
and 0E1H to WDTRST. WDTRST is a write only register. The WDT
counter cannot be read or written. When the WDT overflows, it will
generate an output RESET pulse at the reset pin (see note below).
The RESET pulse duration is 98
×
T
OSC
(6-clock mode; 196 in
12-clock mode), where T
OSC
= 1/f
OSC
. To make the best use of the
WDT, it should be serviced in those sections of code that will
periodically be executed within the time required to prevent a WDT
reset.
相關(guān)PDF資料
PDF描述
P89C51RD2HBP 80C51 8-bit Flash microcontroller family
P89C51RD2HXX 80C51 8-bit Flash microcontroller family
P89C51UBAA 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash
P89C51UFAA BUILDERS BOX SET;
P89C51UFBB WIRE CUTTING/STRIPPING PLIERWIRE CUTTING/STRIPPING PLIER; Area, wire size min:0.5mm2; Area, wire size max:6mm2; Capacity, cutting:2.8mm; Stripping Capacity:20AWG
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
P89C51RC2HFP 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
P89C51RC2HXX 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:80C51 8-bit Flash microcontroller family
P89C51RCIN 制造商: 功能描述: 制造商:NA 功能描述: 制造商:PHILS 功能描述: 制造商:undefined 功能描述:
P89C51RD+ 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:80C51 8-bit Flash microcontroller family 32K/64K ISP FLASH with 512.1K RAM
P89C51RD+IA 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:80C51 8-bit Flash microcontroller family 32K/64K ISP FLASH with 512.1K RAM
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*