參數(shù)資料
型號: P89C51RB2FB
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
中文描述: 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP44
封裝: 10 X 10 X 1.75 MM, PLASTIC, SOT-307-2, QFP-44
文件頁數(shù): 17/52頁
文件大小: 289K
代理商: P89C51RB2FB
Philips Semiconductors
Preliminary specification
89C51RB2/89C51RC2/
89C51RD2
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
1999 Sep 23
17
SCON
Address = 98H
Reset Value = 0000 0000B
SM0/FE
7
SM1
6
SM2
5
REN
4
TB8
3
RB8
2
Tl
1
Rl
0
Bit Addressable
(SMOD0 = 0/1)*
Symbol
Function
FE
Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.
Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
Serial Port Mode Bit 1
SM0
SM1
Mode
Description
Baud Rate**
0
0
0
shift register
f
OSC
/6 (6 clock mode) or f
OSC
/12 (12 clock mode)
0
1
1
8-bit UART
variable
1
0
2
9-bit UART
f
OSC
/32 or f
OSC
/16 (6 clock mode) or
f
OSC
/64 or f
OSC
/32 (12 clock mode)
1
1
3
9-bit UART
variable
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the
received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.
In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a
Given or Broadcast Address. In Mode 0, SM2 should be 0.
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.
In Mode 0, RB8 is not used.
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in
the other modes, in any serial reception (except see SM2). Must be cleared by software.
SM0
SM1
SM2
REN
TB8
RB8
Tl
Rl
NOTE:
*SMOD0 is located at PCON6.
**f
OSC
= oscillator frequency
SU01255
Bit:
Figure 7. SCON: Serial Port Control Register
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