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參數(shù)資料
| 型號： | P89C51RB2FA |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
| 中文描述： | 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, SOT-187-2, LCC-44 |
| 文件頁數(shù)： | 31/52頁 |
| 文件大?。?/td> | 289K |
| 代理商： | P89C51RB2FA |
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Philips Semiconductors
Preliminary specification
89C51RB2/89C51RC2/
89C51RD2
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
1999 Sep 23
31
ERAM
256 or 768 BYTES
UPPER
128 BYTES
INTERNAL RAM
LOWER
128 BYTES
INTERNAL RAM
SPECIAL
FUNCTION
REGISTER
100
FF
00
FF
00
80
80
EXTERNAL
DATA
MEMORY
FFFF
0000
SU01293
Figure 28. Internal and External Data Memory Address Space with EXTRAM = 0
HARDWARE WATCHDOG TIMER (ONE-TIME ENABLED WITH RESET-OUT FOR 89C51RB2/RC2/RD2)
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit
counter and the WatchDog Timer reset (WDTRST) SFR. The WDT is disabled at reset. To enable the WDT, user must write 01EH and 0E1H in
sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running and
there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an
output reset HIGH pulse at the RST-pin (see the note below).
Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, the user needs to
service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH) and this
will reset the device. When WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset
the WDT at least every 16383 machine cycles. To reset the WDT, the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only
register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the reset pin (see note
below). The RESET pulse duration is 98
×
T
OSC
(6 clock mode; 196 in 12 clock mode), where T
OSC
= 1/f
OSC
. To make the best use of the WDT, it
should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.
ABSOLUTE MAXIMUM RATINGS
1, 2, 3
PARAMETER
RATING
UNIT
°
C
°
C
V
Operating temperature under bias
0 to +70 or –40 to +85
Storage temperature range
–65 to +150
Voltage on EA/V
PP
pin to V
SS
Voltage on any other pin to V
SS
Maximum I
OL
per I/O pin
Power dissipation (based on package heat transfer limitations, not device power consumption)
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V
SS
unless otherwise noted.
4. Programming is guaranteed from 0
°
C to T
max
for all devices.
0 to +13.0
–0.5 to +6.5
V
15
mA
1.5
W
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P89C51RB2FB | 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
| P89C51RB2FP | 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
| P89C51RB2HFA | 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
| P89C51RB2HFB | 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
| P89C51RB2HFP | 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P89C51RB2FB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
| P89C51RB2FP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
| P89C51RB2H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
| P89C51RB2HBA | 制造商:NXP Semiconductors 功能描述:8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQCC44 |
| P89C51RB2HBB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
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