參數(shù)資料
型號: P87LPC759BN
廠商: NXP Semiconductors N.V.
英文描述: Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP
中文描述: 低功耗,低價格,低引腳數(shù)(14針),1字節(jié)檢察官辦公室微控制器
文件頁數(shù): 7/9頁
文件大小: 168K
代理商: P87LPC759BN
Philips Semiconductors
Preliminary data
P87LPC759
Low power, low price, low pin count (14 pin)
microcontroller with 1 kbyte OTP
2002 Mar 21
5
PIN DESCRIPTION
MNEMONIC
PIN NO.
TYPE
NAME AND FUNCTION
P0.3–P0.6
10, 12–14
I/O
Port 0:
Port 0 is a 4-bit I/O port with a user-configurable output type. Port 0 latches are con-
figured in the quasi-bidirectional mode and have either ones or zeros written to them during
reset, as determined by the PRHI bit in the UCFG1 configuration byte. The operation of port
0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to the section on I/O port configuration and the DC Electri-
cal Characteristics for details.
The Keyboard Interrupt feature operates with port 0 pins.
P1.0–P1.3
P1.5, P1.7
1–2
6–9
I/O
Port 1:
Port 1 is an 6-bit I/O port with a user-configurable output type, except for three pins
as noted below. Port 1 latches are configured in the quasi-bidirectional mode and have ei-
ther ones or zeros written to them during reset, as determined by the PRHI bit in the UCFG1
configuration byte. The operation of the configurable port 1 pins as inputs and outputs de-
pends upon the port configuration selected. Each of the configurable port pins are pro-
grammed independently. Refer to the section on I/O port configuration and the DC Electrical
Characteristics for details.
Port 1 also provides various special functions as described below.
P1.2
T0
Timer/counter 0 external count input or overflow output.
When configured as an output, P1.2 is open drain.
7
I/O
O
6
I
O
P1.3
INT0
External interrupt 0 input.
When configured as an output, P1.3 is open drain.
2
I
P1.5
RST
External Reset input (if selected via EPROM configuration). A
low on this pin resets the microcontroller, causing I/O ports and
peripherals to take on their default states, and the processor
begins execution at address 0. When used as a port pin, P1.5 is
a Schmitt trigger input only.
Port 2:
Port 2 is a 2-bit I/O port with a user-configurable output type. Port 2 latches are con-
figured in the quasi-bidirectional mode and have either ones or zeros written to them during
reset, as determined by the PRHI bit in the UCFG1 configuration byte. The operation of port
2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to the section on I/O port configuration and the DC Electri-
cal Characteristics for details.
Port 2 also provides various special functions as described below.
P2.0–P2.1
4, 5
I/O
5
O
P2.0
X2
Output from the oscillator amplifier (when a crystal oscillator
option is selected via the EPROM configuration).
CPU clock divided by 6 clock output when enabled via SFR bit
and in conjunction with internal RC oscillator or external clock
input.
CLKOUT
4
I
P2.1
X1
Input to the oscillator circuit and internal clock generator circuits
(when selected via the EPROM configuration).
V
SS
V
DD
3
I
Ground:
0 V reference.
11
I
Power Supply:
This is the power supply voltage for normal operation as well as Idle and
Power Down modes.
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P87LPC760 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP
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P87LPC760BN 功能描述:8位微控制器 -MCU 1K/128 OTP 2.7-6V COMM DIP RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT