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參數(shù)資料
| 型號： | P87C575EBBB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 80C51 8-bit microcontroller family 8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer |
| 中文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44 |
| 文件頁數(shù)： | 5/40頁 |
| 文件大?。?/td> | 383K |
| 代理商： | P87C575EBBB |
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Philips Semiconductors
Product specification
80C575/83C575/
87C575
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
1998 May 01
5
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC
DIP
LCC
QFP
TYPE
NAME AND FUNCTION
V
SS
V
CC
20
22
16
I
Ground:
0V reference.
40
44
38
I
Power Supply:
This is the power supply voltage for normal, idle, and power-down
operation.
P0.0-0.7
39-32
43-36
37-30
I/O
Port 0:
Port 0 is an open-drain bidirectional I/O port. Port 0 pins that have 1s written to them
float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and data memory. In this
application, it uses strong internal pull-ups when emitting 1s. Port 0 also receives code
bytes during EPROM programming and outputs code bytes during program verification.
External pull-ups are required during program verification. During reset, port 0 will be
asynchronously driven low and will remain low until written to by software. All port 0 pins
have Schmitt trigger inputs with 200mV hysteresis. A weak pulldown on port 0 guarantees
positive leakage current (see DC Electrical Characteristics: I
L1
).
Port 1:
Port 1 is an 8-bit bidirectional I/O port. Port 1 pins have internal pull-ups such that
pins that have 1s written to them can be used as inputs but will source current when
externally pulled low (see DC Electrical Characteristics: I
IL
). Port 1 receives the low-order
address byte during program memory verification and EPROM programming. During reset,
port 1 will be asynchronously driven low and will remain low until written to by software. All
port 1 pins have Schmitt trigger inputs with 50mV hysteresis. Port 1 pins also serve
alternate functions as follows:
P1.0
T2
Timer 2 external I/O – clockout (programmable)
CMP0+
Comparator 0 positive input
P1.1
T2EX
Timer 2 capture input
CMP0-
Comparator 0 negative input
P1.2
ECI
PCA count input
P1.3
CEX0
PCA module 0 external I/O
CMP0
Comparator 0 output
P1.4
CEX1
PCA module 1 external I/O
CMP1
Comparator 1 output
P1.5
CEX2
PCA module 2 external I/O
CMP2
Comparator 2 output
P1.6
CEX3
PCA module 3 external I/O
CMP3
Comparator 3 output
P1.7
CEX4
PCA module 4 external I/O
P1.0-P1.7
1-8
2-9
40-44
1-3
I/O
1
2
40
I/O
2
3
41
I
3
4
4
5
42
43
I
I/O
5
6
44
I/O
6
7
1
I/O
7
8
2
I/O
8
9
3
I/O
P2.0-P2.7
21-28
24-31
18-25
I/O
Port 2:
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them can be used as inputs, but will source current when externally pulled low
(see DC Electrical Characteristics: I
). Port 2 emits the high-order address byte during
accesses to external program and data memory that use 16-bit addresses (MOVX
@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. Port 2
receives the high-order address byte during program verification and EPROM programming.
During reset, port 2 will be asynchronously driven low and will remain low until written to by
software. Port 2 can be made open drain by writing to the P2OD register (AIH). In open
drain mode, weak pulldowns on port 2 guarantee positive leakage current (see DC
Electrical Characteristics I
L1
).
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins except P3.1
that have 1s written to them can be used as inputs but will source current when externally
pulled low (see DC Electrical Characteristics: I
IL
). P3.1 will be a high impedance pin except
while transmitting serial data, in which case the strong pull-up will remain on continuously
when outputting a 1 level. The P3.1 output drive level when transmitting can be set to one of
two levels by the writing to the P3.1 register bit. During reset all pins (except P3.1) will be
asynchronously driven low and will remain low until written to by software. All port 3 pins
have Schmitt trigger inputs with 200mV hysteresis, except P3.2 and P3.3, which have 50mV
hysteresis. Port 3 pins serve alternate functions as follows:
P3.0-P3.7
10-17
11,
13-19
5,
7-13
I/O
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