參數(shù)資料
型號： P87C52SBBB,557
廠商： NXP Semiconductors
文件頁數(shù)： 17/38頁
文件大?。?/td> 0K
描述： IC 80C51 MCU 8K OTP 44-PQFP
產(chǎn)品培訓模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標準包裝： 480
系列： 87C
核心處理器： 8051
芯體尺寸： 8-位
速度： 16MHz
連通性： EBI/EMI，UART/USART
外圍設備： POR
輸入/輸出數(shù)： 32
程序存儲器容量： 8KB（8K x 8）
程序存儲器類型： OTP
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 44-QFP
包裝： 托盤
產(chǎn)品目錄頁面： 705 (CN2011-ZH PDF)
其它名稱： 568-1248
935252880557
P87C52SBBB
Philips Semiconductors
Product specification
80C51/87C51/80C52/87C52
80C51 8-bit microcontroller family
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
2000 Aug 07
24
AC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = +2.7 V to +5.5 V, VSS = 0 V1, 2, 3
16 MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1/tCLCL
14
Oscillator frequency5
Speed versions :S
3.5
16
MHz
tLHLL
14
ALE pulse width
85
2tCLCL–40
ns
tAVLL
14
Address valid to ALE low
22
tCLCL–40
ns
tLLAX
14
Address hold after ALE low
32
tCLCL–30
ns
tLLIV
14
ALE low to valid instruction in
150
4tCLCL–100
ns
tLLPL
14
ALE low to PSEN low
32
tCLCL–30
ns
tPLPH
14
PSEN pulse width
142
3tCLCL–45
ns
tPLIV
14
PSEN low to valid instruction in
82
3tCLCL–105
ns
tPXIX
14
Input instruction hold after PSEN
0
ns
tPXIZ
14
Input instruction float after PSEN
37
tCLCL–25
ns
tAVIV 4
14
Address to valid instruction in
207
5tCLCL–105
ns
tPLAZ
14
PSEN low to address float
10
ns
Data Memory
tRLRH
15, 16
RD pulse width
275
6tCLCL–100
ns
tWLWH
15, 16
WR pulse width
275
6tCLCL–100
ns
tRLDV
15, 16
RD low to valid data in
147
5tCLCL–165
ns
tRHDX
15, 16
Data hold after RD
0
ns
tRHDZ
15, 16
Data float after RD
65
2tCLCL–60
ns
tLLDV
15, 16
ALE low to valid data in
350
8tCLCL–150
ns
tAVDV
15, 16
Address to valid data in
397
9tCLCL–165
ns
tLLWL
15, 16
ALE low to RD or WR low
137
239
3tCLCL–50
3tCLCL+50
ns
tAVWL
15, 16
Address valid to WR low or RD low
122
4tCLCL–130
ns
tQVWX
15, 16
Data valid to WR transition
13
tCLCL–50
ns
tWHQX
15, 16
Data hold after WR
13
tCLCL–50
ns
tQVWH
16
Data valid to WR high
287
7tCLCL–150
ns
tRLAZ
15, 16
RD low to address float
0
ns
tWHLH
15, 16
RD or WR high to ALE high
23
103
tCLCL–40
tCLCL+40
ns
External Clock
tCHCX
18
High time
20
tCLCL–tCLCX
ns
tCLCX
18
Low time
20
tCLCL–tCHCX
ns
tCLCH
18
Rise time
20
ns
tCHCL
18
Fall time
20
ns
Shift Register
tXLXL
17
Serial port clock cycle time
750
12tCLCL
ns
tQVXH
17
Output data setup to clock rising edge
492
10tCLCL–133
ns
tXHQX
17
Output data hold after clock rising edge
8
2tCLCL–117
ns
tXHDX
17
Input data hold after clock rising edge
0
ns
tXHDV
17
Clock rising edge to input data valid
492
10tCLCL–133
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. Interfacing the 87C51, 80C51, 87C52, or 80C52 to devices with float times up to 45 ns is permitted. This limited bus contention will not
cause damage to Port 0 drivers.
4. See application note AN457 for external memory interface.
5. Parts are guaranteed to operate down to 0 Hz. When an external clock source is used, the RST pin should be held high for a minimum of
20
s for power-on or wakeup from power down.
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