參數(shù)資料
型號： P87C51RA2
廠商： NXP Semiconductors N.V.
英文描述： 80C51 8-bit microcontroller family
中文描述： 80C51的8位單片機(jī)系列
文件頁數(shù)： 22/34頁
文件大?。?/td> 394K
代理商： P87C51RA2
2001 Apr 06
22
Philips Semiconductors
Preliminary specification
P87C51MB2/P87C51MC2
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
Notes:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause
damage to Port 0 drivers.
4. Parts are tested down to 2 MHz, but are guaranteed to operate down to 0Hz.
Shift Register
t
XLXL
7
Serial port clock cycle time
Output data setup to clock rising
edge
Output data hold after clock rising
edge
Input data hold after clock rising
edge
Clock rising edge to input data valid
6t
CLCL
500
6t
CLCL
250
ns
t
QVXH
7
5t
CLCL
-221
195
5t
CLCL
-110
98
ns
t
XHQX
7
t
CLCL
-50
34
t
CLCL
-25
17
ns
t
XHDX
7
0
0
0
0
ns
t
XHDV
SPI Interface
7
5t
CLCL
-222
195
5t
CLCL
-111
97
ns
f
SPI
Operating frequency
- 3.0MHz
- 6.0MHz
Cycle time
- 3.0MHz
- 6.0MHz
Enable lead time (Slave)
- 3.0MHz
- 6.0MHz
Enable lag time (Slave)
- 3.0MHz
- 6.0MHz
SPICLK high time
- Master
- Slave
SPICLK low time
- Master
- Slave
MHz
0
-
3.0
-
0
-
3.0
-
0
0
3.0
6.0
0
0
3.0
6.0
t
SPICYC
8, 9, 10, 11
ns
333
-
333
-
333
166
333
166
t
SPILEAD
10, 11
ns
TBD
-
TBD
-
TBD
TBD
TBD
TBD
t
SPILAG
10, 11
ns
TBD
-
TBD
-
TBD
TBD
TBD
TBD
t
SPICLKH
8, 9, 10, 11
ns
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
t
SPICLKL
8, 9, 10, 11
ns
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
t
SPIDSU
t
SPIDH
t
SPIA
8, 9, 10, 11 Data setup time (Master or Slave)
ns
8, 9, 10, 11 Data hold time (Master or Slave)
TBD
TBD
TBD
TBD
ns
10, 11
Access time (Slave)
Disable time (Slave)
- 3.0MHz
- 6.0MHz
Enable to output data valid
- 3.0MHz
- 6.0MHz
8, 9, 10, 11 Output data hold time
Rise time
- SPI outputs (SPICLK,MOSI, MISO)
- SPI inputs (SPICLK,MOSI, MISO,
SS)
Fall time
- SPI outputs (SPICLK,MOSI, MISO)
- SPI inputs (SPICLK,MOSI, MISO,
SS)
TBD
TBD
TBD
TBD
ns
t
SPIDIS
10, 11
ns
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
t
SPIDV
8, 9, 10, 11
ns
TBD
-
TBD
-
TBD
TBD
TBD
TBD
t
SPIOH
0
0
0
0
ns
t
SPIR
8, 9, 10, 11
ns
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
t
SPIF
8, 9, 10, 11
ns
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
SYMBOL FIGURE(S)
PARAMETER
2.7V < VDD < 5.5V
4.5V < VDD < 5.5V
UNIT
Variable Clock
4
f
OSC
=12MHz
4
MIN
Variable Clock
4
f
OSC
=24MHz
4
MIN
MIN
MAX
MAX
MIN
MAX
MAX
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