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參數(shù)資料
| 型號(hào)： | P87C51FB-JN |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 80C51 8-bit microcontroller family 8K.64K/256.1K OTP/ROM/ROMless, low voltage 2.7V.5.5V, low power, high speed 33 MHz |
| 中文描述： | 8-BIT, OTPROM, 33 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, PLASTIC, MO-015, SOT-129-1, DIP-40 |
| 文件頁(yè)數(shù)： | 19/34頁(yè) |
| 文件大小： | 394K |
| 代理商： | P87C51FB-JN |
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2001 Apr 06
19
Philips Semiconductors
Preliminary specification
P87C51MB2/P87C51MC2
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
DC ELECTRICAL CHARACTERISTICS
V
DD
= 2.7V to 5.5V unless otherwise specified;
T
amb
= 0 to +70°C for commercial, unless otherwise specified.
Notes:
1. Typical ratings are not guaranteed. The values listed are at room temperature (+25°C), 5V, unless otherwise stated.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
OL
of ALE and ports 1, 3 and 4.
The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0
transitions during bus operations. In the worst cases (capacitive loading>100 pF), the noise pulse on the ALE pin may exceed
0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger
STROBE input. I
OL
can exceed these conditions provided that no single output sinks more than 5mA and no more than two
outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the V
OH
on ALE and PSEN to momentarily fall below the V
DD
-0.7V
specification when the address bits are stabilizing.
4. Pins of ports 1, 2, 3 and 4 source a transition current when they are being externally driven from 1 to 0. The transition current
reaches its maximum value when V
IN
is approximately 2 V for 4.5V < V
DD
< 5.5V.
5. See Figures 13 through 16 for I
CC
test conditions. f
OSC
is the oscillator frequency in MHz.
6. This value applies to T
amb
= 0°C to +70°C.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
TYP
1
UNIT
MIN
-0.5
MAX
V
IL
Input low voltage
Input high voltage (ports 0, 1, 2, 3,
4, EA)
Input high voltage, XTAL1, RST
Output low voltage, ports 1, 2, 3, 4
8
V
DD
= 2.7V, I
OL
= 1.6mA
Output low voltage, port 0, ALE,
PSEN
7,8
0.2V
DD
-0.1
V
V
IH
0.2V
DD
+0.9
V
DD
+0.5
V
V
IH1
V
OL
0.7V
DD
V
DD
+0.5
0.4
V
V
V
OL1
V
DD
= 2.7V, I
OL
= 3.2mA
0.4
V
V
OH
Output high voltage, ports 1, 2, 3, 4
V
DD
= 4.5V, I
OH
= -30μA
V
DD
= 2.7V, I
OH
= -10μA
V
DD
- 0.7
V
V
OH1
Output high voltage (port 0 in
external bus mode), ALE
9
, PSEN
3
V
DD
= 2.7V, I
OH
= -3.2mA
Logical 0 input current, ports 1, 2,
3, 4
Logical 1 -to-0 transition current,
ports 1, 2, 3, 4
8
Input leakage current, port 0
Power supply current
V
DD
- 0.7
V
I
IL
V
IN
= 0.4V
-1
-75
μA
I
TL
4.5V < V
DD
< 5.5V,
V
IN
= 2.0V, See Note 4
0.45 < V
IN
< V
DD
-0.3
-650
μA
I
L1
±10
μA
I
CC
Active mode (see Note 5)
V
DD
= 5.5V
7 +
2.7 /MHz × f
OSC
4 +
1.3 /MHz × f
OSC
4 +
1.3 /MHz × f
OSC
1 +
1.0 /MHz × f
OSC
mA
V
DD
= 3.6V
Idle mode (see Note 5)
V
DD
= 5.5V
mA
V
DD
= 3.6V
Power-down mode or clock
stopped (see Figure 16 for
conditions)
Internal reset pull-down resistor
Pin capacitance
10
(except EA)
V
DD
= 5.0V
V
DD
= 5.5V
20
μA
100
μA
R
RST
C
10
40
225
15
k
pF
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