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    參數(shù)資料
    型號(hào): P87C51FB–4A
    廠商: NXP Semiconductors N.V.
    英文描述: 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless. low voltage 2.7V-5.5V). low power. high speed (33 MHz)
    中文描述: 80C51的8位單片機(jī)系列8K-64K/256-1K檢察官辦公室/光盤/無ROM。低電壓為2.7V至5.5V)。低功耗。高速(33兆赫)
    文件頁(yè)數(shù): 13/34頁(yè)
    文件大小: 394K
    代理商: P87C51FB–4A
    2001 Apr 06
    13
    Philips Semiconductors
    Preliminary specification
    P87C51MB2/P87C51MC2
    80C51 8-bit microcontroller family with extended memory
    64KB/96KB OTP with 2KB/3KB RAM
    FUNCTIONAL DESCRIPTION
    The following paragraphs briefly describe the features of the P87C51Mx2. For more detailed information, please refer to the
    P87C51Mx2 User Manual or the 51MX Architecture Reference.
    INTERRUPTS
    Table 1 summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits, polling priority, and whether each
    interrupt may wake up the CPU from Power Down mode.
    Description
    Interrupt
    Flag Bit(s)
    IE0
    TF0
    IE1
    TF1
    TI_0 & RI_0
    5
    RI_0
    5
    TF2, EXF2
    CF, CCFn*
    TI_1 & RI_1
    6
    RI_1
    6
    TI_0
    TI_1
    SPI
    Vector
    Address
    0003h
    000Bh
    0013h
    001Bh
    Interrupt
    Enable Bit(s)
    EX0 (IEN0.0)
    ET0 (IEN0.1)
    EX1 (IEN0.2)
    ET1 (IEN0.3)
    Interrupt
    Priority
    IP0H.0, IP0.0
    IP0H.1, IP0.1
    IP0H.2, IP0.2
    IP0H.3, IP0.3
    Polling
    Priority
    1 (highest)
    2
    3
    4
    Power Down
    Wakeup
    Yes
    No
    Yes
    No
    External Interrupt 0
    Timer 0 Interrupt
    External Interrupt 1
    Timer 1 Interrupt
    Serial Port 0 Tx and Rx
    1,5
    Serial Port 0 Rx
    1,5
    Timer 2 Interrupt
    PCA interrupt
    Serial Port 1 Tx and Rx
    2,6
    Serial Port 1 Rx
    2,6
    Serial Port 0 Tx
    3
    Serial Port 1 Tx
    4
    SPI Interrupt
    0023h
    ES0(IEN0.4)
    IP0H.4, IP0.4
    6
    No
    002Bh
    0033h
    ET2 (IEN0.5)
    EC (IEN0.6)
    IP0H.5, IP0.5
    IP0H.6, IP0.6
    7
    5
    No
    No
    0053h
    ES1 (IEN1.0)
    IP1H.0, IP1.0
    11
    No
    003Bh
    0043h
    004Bh
    005Bh
    0063h
    006Bh
    0073h
    EI10 (IEN1.1)
    EI11 (IEN1.2)
    EI11 (IEN1.3)
    EI12 (IEN1.4)
    EI13 (IEN1.5)
    EI13 (IEN1.6)
    EI14 (IEN1.7)
    IP1H.1, IP1.1
    IP1H.2, IP1.2
    IP1H.3, IP1.3
    IP1H.4, IP1.4
    IP1H.5, IP1.5
    IP1H.6, IP1.6
    IP1H.7, IP1.7
    8
    9
    No
    No
    No
    No
    No
    No
    No
    10
    12
    13
    14
    Reserved
    15 (lowest)
    1. S0STAT.5 = 0 selects combined Serial Port 0 Tx and Rx interrupt; S0STAT.5 = 1 selects Serial Port 0 Rx interrupt only (and
    TX interrupt will be different, see Note 3 below).
    2. S1STAT.5 = 0 selects combined Serial Port 1 Tx and Rx interrupt; S1STAT.5 = 1 selects Serial Port 1 Rx interrupt only (and
    TX interrupt will be different, see Note 4 below).
    3. This interrupt is used as Serial Port 0 Tx interrupt if and only if S0STAT.5 = 1, and is disabled otherwise.
    4. This interrupt is used as Serial Port 1 Tx interrupt if and only if S1STAT.5 = 1, and is disabled otherwise.
    5. If S0STAT.0 = 1, the following Serial Port 0 additional flag bits can cause this interrupt: FE_0, BR_0, OE_0.
    6. If S1STAT.0 = 1, the following Serial Port 1 additional flag bits can cause this interrupt: FE_1, BR_1, OE_1.
    Table 1: Summary of Interrupts
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