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參數(shù)資料
| 型號： | P87C32X2 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 8-bit microcontroller family 4K/8K/16K/32K ROM/OTP 128B/256B RAM low voltage 2.7 to 5.5 V, low power, high speed 30/33 MHz |
| 中文描述： | 80C51的8位單片機(jī)系列4K/8K/16K/32K的ROM / RAM的檢察官辦公室128B/256B低電壓2.7至5.5 V，低功耗，高速33分之30兆赫 |
| 文件頁數(shù)： | 38/62頁 |
| 文件大?。?/td> | 403K |
| 代理商： | P87C32X2 |
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Philips Semiconductors
Product data
P80C3xX2; P80C5xX2;
P87C5xX2
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
2003 Jan 24
38
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0
°
C to +70
°
C or –40
°
C to +85
°
C;
V
CC
= 2.7 V to 5.5 V
; V
SS
= 0 V (16 MHz max. CPU clock)
SYMBOL
PARAMETER
TEST
CONDITIONS
LIMITS
UNIT
MIN
–0.5
–0.5
0.2 V
CC
+0.9
0.7 V
CC
–
–
V
CC
– 0.7
V
CC
– 0.7
V
CC
– 0.7
TYP
1
MAX
0.2 V
CC
–0.1
0.7 V
CC
V
CC
+0.5
V
CC
+0.5
0.4
0.4
–
–
–
V
IL
Input low voltage
11
4.0 V < V
CC
< 5.5 V
2.7 V < V
CC
< 4.0 V
–
–
V
CC
= 2.7 V; I
OL
= 1.6 mA
2
V
CC
= 2.7 V; I
OL
= 3.2 mA
2
V
CC
= 2.7 V; I
OH
= –20 A
V
CC
= 4.5 V; I
OH
= –30 A
V
CC
= 2.7 V; I
OH
= –3.2 mA
V
V
V
V
V
V
V
V
V
V
IH
V
IH1
V
OL
V
OL1
V
OH
Input high voltage (ports 0, 1, 2, 3, EA)
Input high voltage, XTAL1, RST
11
Output low voltage, ports 1, 2,
8
Output low voltage, port 0, ALE, PSEN
8, 7
Output high voltage, ports 1, 2, 3
3
V
OH1
Output high voltage (port 0 in external bus
mode), ALE
9
, PSEN
3
Logical 0 input current, ports 1, 2, 3
Logical 1-to-0 transition current, ports 1, 2, 3
6
Input leakage current, port 0
Power supply current (see Figure 34 and
Source Code):
Active mode @ 16 MHz
Idle mode @ 16 MHz
Power-down mode or clock stopped
(see Figure 30 for conditions)
12
I
IL
I
TL
I
LI
I
CC
V
IN
= 0.4 V
V
IN
= 2.0 V; See note 4
0.45 < V
IN
< V
CC
– 0.3
–1
–
–
–50
–650
±
10
A
A
A
A
A
A
T
amb
= 0
°
C to 70
°
C
30
T
amb
= –40
°
C to +85
°
C
–
–
–
3
50
A
V
RAM
R
RST
C
IO
RAM keep-alive voltage
Internal reset pull-down resistor
Pin capacitance
10
(except EA)
1.2
40
–
V
k
pF
225
15
NOTES:
1. Typical ratings are not guaranteed. Values listed are based on tests conducted on limited number of samples at room temperature.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
OL
s of ALE and ports 1 and 3. The noise is
due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations.
In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to
qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
OL
can exceed these conditions provided
that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the V
OH
on ALE and PSEN to momentarily fall below the V
CC
–0.7 specification when the
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V
IN
is approximately 2 V.
5. See Figures 36 through 39 for I
CC
test conditions and Figure 34 for I
CC
vs. Frequency
12-clock mode characteristics:
Active mode (operating):
I
CC
= 1.0 mA + 0.9 mA
×
FREQ.[MHz]
Active mode (reset):
I
CC
= 7.0 mA + 0.5 mA x FREQ.[MHz]
Idle mode:
I
CC
= 1.0 mA + 0.18 mA x FREQ.[MHz]
6. This value applies to T
= 0
°
C to +70
°
C. For T
= –40
°
C to +85
°
C, I
= –750 A.
7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
8. Under steady state (non-transient) conditions, I
must be externally limited as follows:
Maximum I
OL
per port pin:
15 mA (*NOTE: This is 85
°
C specification.)
Maximum I
OL
per 8-bit port:
26 mA
Maximum total I
OL
for all outputs:
71 mA
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
9. ALE is tested to V
OH1
, except when ALE is off then V
OH
is the voltage specification.
10.Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF
(except EA is 25 pF).
11. To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin, and a nominal 15 ns glitch rejection
circuitry has been added to the INT0 and INT1 pins. Previous devices provided only an inherent 5 ns of glitch rejection.
12.Power down mode for 3 V range: Commercial Temperature Range – typ: 0.5 A, max. 20 A; Industrial Temperature Range – typ. 1.0 A,
max. 30 A;
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