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參數(shù)資料
| 型號： | P83CE598FHB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-bit microcontroller with CAN controller(帶CAN控制器的8位微控制器) |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數(shù)： | 62/108頁 |
| 文件大?。?/td> | 661K |
| 代理商： | P83CE598FHB |
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1996 Jun 27
62
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
13.6.8.3
CRC Error
To ensure the validity of a transmitted message all
receivers perform a CRC check. Therefore, in addition to
the (destuffed) information digits (Start-Of-Frame up to
Data Field), every message includes some control digits
(CRC Sequence; generated by the transmitting
CAN-controller of the respective message) used for error
detection.
The code used by all CAN-controllers is a (shortened)
BCH code, extended by a parity check and has the
following attributes:
127 bits as maximum length of the code.
112 bits as maximum number of information digits
(max. 83 bits are used by the CAN-controller).
Length of the CRC Sequence amounts to 15 bits.
Hamming distance d = 6.
As a result, ‘(d
1)’ random errors are detectable (some
exceptions exist).
The CRC Sequence is determined (calculated) by the
following procedure:
1.
The destuffed bit stream consisting of Start-Of-Frame
up to the Data Field (if present) is interpreted as
polynomial with coefficients 0 or 1.
2.
This polynomial is divided (modulo-2) by the following
generator polynomial, which includes a parity check:
f x)
x
14
x
9
x
8
x
6
+
+
+
+
(
=
(x + 1) = 1100010110011001 B.
The remainder of this polynomial division is the
CRC sequence.
3.
Burst errors are detected up to a length of 15
[
degree of f(x)
]
. Multiple errors (number of disturbed bits at
least d = 6) are not detected with a residual error
probability of
2
15
3
10
5
×
(
)
by CRC check only.
13.6.8.4
Form Error
Form Errors result from violations of the fixed form of the
following bit fields:
CRC Delimiter
Acknowledge Delimiter
End-Of-Frame
Error Delimiter
Overload Delimiter.
During the transmission of these bit fields an error
condition is recognized if a dominant bit level instead of a
recessive one is detected.
x
5
x
4
x
2
x
1
+
+
+
+
)
–
–
13.6.8.5
Acknowledgement Error
This is detected by a transmitter whenever it does not
monitor a dominant bit during the Acknowledge Slot.
13.6.8.6
Error detection by an Error Flag from
another CAN-controller
The detection of an error is signalled by transmitting an
Error Flag. An Active Error Flag causes a Stuff Error, a Bit
Error or a Form Error at all other CAN-controllers.
13.6.8.7
Error Detection Capabilities
Errors which occur at all CAN-controllers (global errors)
are 100% detected. For local errors, i.e. for errors
occurring at some CAN-controllers only, the shortened
BCH code, extended by a parity check, has the following
error detection capabilities:
Up to five single Bit Errors are 100% detected, even if
they are distributed randomly within the code.
All single Bit Errors are detected if their total number
(within the code) is odd.
The residual error probability of the CRC check amounts
to (3
×
10
5
). As an error may be detected not only by
CRC check but also by other detection processes
described above the residual error probability is several
magnitudes less than (3
×
10
5
).
13.6.9
E
RROR CONFINEMENT DEFINITIONS
13.6.9.1
Bus-OFF
A CAN-controller which has too many unsuccessful
transmissions, relative to the number of successful
transmissions, will enter the Bus-OFF state. It remains in
this state, neither receiving nor transmitting messages
until the Reset Request bit is set LOW (absent) and both
Error Counters set to 0 (see Section 13.6.10).
13.6.9.2
Acknowledge
A CAN-controller which has received a valid message
correctly, indicates this to the transmitter by transmitting a
dominant bit level on the bus during the Acknowledge Slot,
independent of accepting or rejecting the message.
13.6.9.3
Error-Active
An error-active CAN-controller in its normal operating state
is able to receive and to transmit normally and also to
transmit an Active Error Flag (see Section 13.6.10).
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