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參數(shù)資料
| 型號： | P83C754EBDDB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 80C51 8-bit microcontroller family 4K/256 OTP/ROM, DAC, comparator, UART, reference |
| 中文描述： | 8-BIT, MROM, MICROCONTROLLER, PDSO28 |
| 封裝： | PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 22/26頁 |
| 文件大小： | 217K |
| 代理商： | P83C754EBDDB |
Philips Semiconductors
Preliminary specification
83C754/87C754
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
1998 Apr 23
22
EPROM PROGRAMMING AND VERIFICATION
T
amb
= 21
°
C to +27
°
C, V
CC
= 5V
±
10%, V
SS
= 0V
SYMBOL
PARAMETER
MIN
MAX
UNIT
1/t
CLCL
t
AVGL1
Oscillator/clock frequency
1.2
16
MHz
Address setup to PGM low
10
μ
s + 24t
CLCL
t
GHAX
Address hold after PGM high
48t
CLCL
t
DVGL
Data setup to PGM low
38t
CLCL
t
DVGL
Data setup to PGM low
38t
CLCL
t
GHDX
Data hold after PGM high
36t
CLCL
t
SHGL
V
PP
setup to PGM low
10
μ
s
t
GHSL
V
PP
hold after PGM
10
μ
s
t
GLGH
t
AVQV2
PGM width
90
110
μ
s
V
PP
low (V
CC
) to data valid
48t
CLCL
t
GHGL
PGM high to PGM low
10
μ
s
t
SYNL
P0.0 (sync pulse) low
4t
CLCL
t
SYNH
P0.0 (sync pulse) high
8t
CLCL
t
MASEL
ASEL high time
13t
CLCL
t
MAHLD
Address hold time
2t
CLCL
t
HASET
Address setup to ASEL
13t
CLCL
t
ADSTA
NOTES:
1. Address should be valid at least 24t
CLCL
before the rising edge of V
PP
.
2. For a pure verify mode, i.e., no program mode in between, t
AVQV
is 14t
CLCL
maximum.
Low address to address stable
13t
CLCL
A0–A10
ADDRESS STROBE
PROGRAMMING
PULSES
V
PP
/V
IH
VOLTAGE
SOURCE
CLK SOURCE
RESET
CLOGIC
87C754
ZDAC/ASEL
XYDACBIAS/PGM
P1.2/V
PP
X1
RST
V
CC
V
SS
P3.0–P3.7
+5V
DATA BUS
SU00667A
A0–A10
Figure 20. Programming Configuration
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