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參數(shù)資料
| 型號： | P83C748EBAA |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC28 |
| 封裝： | PEDESTAL, PLASTIC, SOT-261-3, LCC-28 |
| 文件頁數(shù)： | 12/18頁 |
| 文件大小： | 131K |
| 代理商： | P83C748EBAA |
Philips Semiconductors
Preliminary specification
83C748/87C748
80C51 8-bit microcontroller family
2K/64 OTP/ROM, low pin count
1999 Apr 15
12
Security Bits
Two security bits, security bit 1 and security bit 2, are provided to
limit access to the USER EPROM and encryption key arrays.
Security bit 1 is the program inhibit bit, and once programmed
performs the following functions:
1. Additional programming of the USER EPROM is inhibited.
2. Additional programming of the encryption key is inhibited.
3. Verification of the encryption key is inhibited.
4. Verification of the USER EPROM and the security bit levels may
still be performed.
(If the encryption key array is being used, this security bit should be
programmed by the user to prevent unauthorized parties from
reprogramming the encryption key to all logical zero bits. Such
programming would provide data during a verify cycle that is the
logical complement of the USER EPROM contents).
Security bit 2, the verify inhibit bit, prevents verification of both the
USER EPROM array and the encryption key arrays. The security bit
levels may still be verified.
Programming and Verifying Security Bits
Security bits are programmed employing the same techniques used
to program the USER EPROM and KEY arrays using serial data
streams and logic levels on port pins indicated in Table 3. When
programming either security bit, it is not necessary to provide
address or data information to the 87C748 on ports 1 and 3.
Verification occurs in a similar manner using the RESET serial
stream shown in Table 3. Port 3 is not required to be driven and the
results of the verify operation will appear on ports 1.6 and 1.7.
Ports 1.7 contains the security bit 1 data and is a logical one if
programmed and a logical zero if not programmed. Likewise, P1.6
contains the security bit 2 data and is a logical one if programmed
and a logical zero if not programmed.
EPROM PROGRAMMING AND VERIFICATION
T
amb
= 21
°
C to +27
°
C, V
CC
= 5V
±
10%, V
SS
= 0V
SYMBOL
PARAMETER
MIN
MAX
UNIT
1/t
CLCL
t
AVGL1
Oscillator/clock frequency
1.2
6
MHz
Address setup to P0.1 (PROG–) low
10
μ
s + 24t
CLCL
t
GHAX
Address hold after P0.1 (PROG–) high
48t
CLCL
t
DVGL
Data setup to P0.1 (PROG–) low
38t
CLCL
t
GHDX
Data hold after P0.1 (PROG–) high
36t
CLCL
t
SHGL
V
PP
setup to P0.1 (PROG–) low
10
μ
s
t
GHSL
V
PP
hold after P0.1 (PROG–)
10
μ
s
t
GLGH
t
AVQV2
P0.1 (PROG–) width
90
110
μ
s
V
PP
low (V
CC
) to data valid
48t
CLCL
t
GHGL
P0.1 (PROG–) high to P0.1 (PROG–) low
10
μ
s
t
MASEL
ASEL high time
13t
CLCL
t
HAHLD
Address hold time
2t
CLCL
t
HASET
Address setup to ASEL
13t
CLCL
t
ADSTA
NOTES:
1. Address should be valid at least 24t
CLCL
before the rising edge of P0.2 (V
PP
).
2. For a pure verify mode, i.e., no program mode in between, t
AVQV
is 14t
CLCL
maximum.
Low address to valid data
48t
CLCL
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P83C748EBDDB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count |
| P83C748EBPN | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count |
| P83C748EFA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| P83C748EFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| P83C749EBAA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count |
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