參數(shù)資料
型號(hào)： P83C654X2FA
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 80C51 8-bit microcontroller family 16 kB OTP/ROM, 256B RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
中文描述： 8-BIT, MROM, 33 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, MS-018, SOT-187-2, LCC-44
文件頁數(shù)： 72/88頁
文件大?。?/td> 497K
代理商： P83C654X2FA
Philips Semiconductors
Product data
P83C654X2/P87C654X2
80C51 8-bit microcontroller family
16 kB OTP/ROM,
256B RAM, low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz)
2004 Apr 20
72
AC ELECTRICAL CHARACTERISTICS (6-CLOCK MODE, 2.7 V TO 5.5 V OPERATION)
T
amb
= 0
°
C to +70
°
C or –40
°
C to +85
°
C; V
CC
=2.7 V to 5.5 V, V
SS
= 0 V
1,2,3,4,5
Symbol
Figure
Parameter
Limits
MIN
16 MHz Clock
MIN
Unit
MAX
MAX
1/t
CLCL
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
Data Memory
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
WHQX
t
QVWH
t
RLAZ
t
WHLH
External Clock
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Shift register
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
I
2
C interface timing
f
SCL
t
BUF
46
41
41
41
41
41
41
41
41
41
41
41
Oscillator frequency
ALE pulse width
Address valid to ALE LOW
Address hold after ALE LOW
ALE LOW to valid instruction in
ALE LOW to PSEN LOW
PSEN pulse width
PSEN LOW to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN LOW to address float
0
t
CLCL
– 10
0.5t
CLCL
– 15
0.5t
CLCL
– 25
–
0.5t
CLCL
– 15
1.5t
CLCL
– 15
–
0
–
–
–
16
–
–
–
2t
CLCL
–55
–
–
1.5t
CLCL
– 55
–
0.5t
CLCL
– 10
2.5t
CLCL
– 50
10
–
52.5
16.25
6.25
–
16.25
78.75
–
0
–
–
–
–
–
–
–
70
–
–
38.75
–
21.25
101.25
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
42
43
42
42
42
42
42
42, 43
42, 43
43
43
43
42
42, 43
RD pulse width
WR pulse width
RD LOW to valid data in
Data hold after RD
Data float after RD
ALE LOW to valid data in
Address to valid data in
ALE LOW to RD or WR LOW
Address valid to WR LOW or RD LOW
Data valid to WR transition
Data hold after WR
Data valid to WR HIGH
RD LOW to address float
RD or WR HIGH to ALE HIGH
3t
CLCL
– 25
3t
CLCL
– 25
–
0
–
–
–
1.5t
CLCL
– 20
2t
CLCL
– 20
0.5t
CLCL
– 30
0.5t
CLCL
– 20
3.5t
CLCL
– 10
–
0.5t
CLCL
– 15
–
–
2.5t
CLCL
– 50
–
t
CLCL
– 20
4t
CLCL
– 55
4.5t
CLCL
– 50
1.5t
CLCL
+ 20
–
–
–
–
0
0.5t
CLCL
+ 15
162.5
162.5
–
0
–
–
–
73.75
105
1.25
11.25
208.75
–
16.25
–
–
106.25
–
42.5
195
231.25
113.75
–
–
–
–
0
46.25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
46
46
46
46
High time
Low time
Rise time
Fall time
0.4t
CLCL
0.4t
CLCL
–
–
t
CLCL
– t
CLCX
t
CLCL
– t
CHCX
5
5
–
–
–
–
–
–
–
–
ns
ns
ns
ns
45
45
45
45
45
Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
6
6t
CLCL
5t
CLCL
–25
t
CLCL
– 15
0
–
–
–
–
–
5t
CLCL
– 133
375
287.5
47.5
0
–
–
–
–
–
179.5
ns
ns
ns
ns
ns
SCL clock frequency
Bus free time between a STOP and START
condition
Hold time (repeated) START condition. After
this period, the first clock pulse is generated
LOW period of the SCL clock
High period of the SCL clock
Set-up time for a repeated START condition
0
4.7
100
–
0
1.3
400
–
kHz
μ
s
t
HD; STA
4.0
–
0.6
–
μ
s
t
LOW
t
HIGH
t
SU; STA
4.7
4.0
4.7
–
–
–
1.3
0.6
0.6
–
–
–
μ
s
μ
s
μ
s
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