參數(shù)資料
型號(hào): P83C654X2BBD
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 80C51 8-bit microcontroller family 16 kB OTP/ROM, 256B RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
中文描述: 8-BIT, MROM, 33 MHz, MICROCONTROLLER, PQFP44
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-389-1, LQFP-44
文件頁數(shù): 35/88頁
文件大?。?/td> 497K
代理商: P83C654X2BBD
Philips Semiconductors
Product data
P83C654X2/P87C654X2
80C51 8-bit microcontroller family
16 kB OTP/ROM,
256B RAM, low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz)
2004 Apr 20
35
INTERNAL BUS
8
BSD7
S1DAT
ACK
SCL
SDA
SHIFT PULSES
SU00969
Figure 26. Serial Input/Output Configuration
SHIFT IN
SDA
SCL
D7
D6
D5
D4
D3
D2
D1
D0
A
SHIFT ACK & S1DAT
ACK
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
A
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
S1DAT
SHIFT BSD7
BSD7
D7
D6
D5
D4
D3
D2
D1
D0
(3)
LOADED BY THE CPU
(1) Valid data in S1DAT
(2) Shifting data in S1DAT and ACK
(3) High level on SDA
SHIFT OUT
SU00970
Figure 27. Shift-in and Shift-out Timing
In the following text, it is assumed that ENS1 = 1.
STA
,
THE
START F
LAG
STA = 1: When the STA bit is set to enter a master mode, the I
2
C
hardware checks the status of the I
2
C-bus and generates a START
condition if the bus is free. If the bus is not free, then I
2
C waits for a
STOP condition (which will free the bus) and generates a START
condition after a delay of a half clock period of the internal serial
clock generator.
If STA is set while I
2
C is already in a master mode and one or more
bytes are transmitted or received, I
2
C transmits a repeated START
condition. STA may be set at any time. STA may also be set when
I
2
C is an addressed slave.
STA = 0: When the STA bit is reset, no START condition or repeated
START condition will be generated.
STO
,
THE
STOP F
LAG
STO = 1: When the STO bit is set while I
2
C is in a master mode, a
STOP condition is transmitted to the I
2
C-bus. When the STOP
condition is detected on the bus, the I
2
C hardware clears the STO
flag. In a slave mode, the STO flag may be set to recover from an
error condition. In this case, no STOP condition is transmitted to the
I
2
C-bus. However, the I
2
C hardware behaves as if a STOP condition
has been received and switches to the defined “not addressed”
slave receiver mode. The STO flag is automatically cleared by
hardware.
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