參數資料
型號： P83C654IBPN
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： CONNECTOR ACCESSORY
中文描述： 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP40
封裝： 0.600 INCH, PLASTIC, DIP-40
文件頁數： 31/88頁
文件大?。?/td> 497K
代理商： P83C654IBPN
Philips Semiconductors
Product data
P83C654X2/P87C654X2
80C51 8-bit microcontroller family
16 kB OTP/ROM,
256B RAM, low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz)
2004 Apr 20
31
V
DD
OTHER DEVICE WITH
I
C-BUS INTERFACE
P8xC654X2
OTHER DEVICE WITH
I
C-BUS INTERFACE
P1.7/SDA
P1.6/SCL
SDA
SCL
I
2
C-bus
R
P
R
P
SU01734
Figure 21. Typical I
2
C-bus configuration
SCL
START
CONDITION
S
SDA
P/S
MSB
ACKNOWLEDGMENT
SIGNAL FROM RECEIVER
CLOCK LINE HELD LOW WHILE
INTERRUPTS ARE SERVICED
1
2
7
8
9
1
2
3–8
ACK
9
ACK
REPEATED IF MORE BYTES
ARE TRANSFERRED
ACKNOWLEDGMENT
SIGNAL FROM RECEIVER
SLAVE ADDRESS
R/W
DIRECTION
BIT
STOP
CONDITION
REPEATED
START
CONDITION
SU00965
Figure 22. Data Transfer on the I
2
C-bus
I
2
C-bus Implementation and Operation:
Figure 23 shows how the
on-chip I
2
C-bus interface is implemented, and the following text
describes the individual blocks.
I
NPUT
F
ILTERS
AND
O
UTPUT
S
TAGES
The input filters have I
2
C-bus compatible input levels. If the input
voltage is less than 1.5 V, the input logic level is interpreted as 0; if
the input voltage is greater than 3.0 V, the input logic level is
interpreted as 1. Input signals are synchronized with the internal
clock (f
OSC
/4), and spikes shorter than three oscillator periods are
filtered out.
The output stages consist of open drain transistors that can sink
3mA at V
OUT
< 0.4 V. These open drain outputs do not have
clamping diodes to V
DD
. Thus, if the device is connected to the
I
2
C-bus and V
DD
is switched off, the I
2
C-bus is not affected.
A
DDRESS
R
EGISTER,
S
1
ADR
This 8-bit special function register may be loaded with the 7-bit slave
address (7 most significant bits) to which the I
2
C-bus will respond
when programmed as a slave transmitter or receiver. The LSB (GC)
is used to enable general call address (00H) recognition.
C
OMPARATOR
The comparator compares the received 7-bit slave address with its
own slave address (7 most significant bits in S1ADR). It also
compares the first received 8-bit byte with the general call address
(00H). If an equality is found, the appropriate status bits are set and
an interrupt is requested.
S
HIFT
R
EGISTER,
S
1
DAT
This 8-bit special function register contains a byte of serial data to
be transmitted or a byte which has just been received. Data in
S1DAT is always shifted from right to left; the first bit to be
transmitted is the MSB (bit 7) and, after a byte has been received,
the first bit of received data is located at the MSB of S1DAT. While
data is being shifted out, data on the bus is simultaneously being
shifted in; S1DAT always contains the last byte present on the bus.
Thus, in the event of lost arbitration, the transition from master
transmitter to slave receiver is made with the correct data in S1DAT.
相關PDF資料
PDF描述
P83C654FBA CMOS single-chip 8-bit microcontroller
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相關代理商/技術參數
參數描述
P83C654IFA 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CMOS single-chip 8-bit microcontroller
P83C654IFAA 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CMOS single-chip 8-bit microcontroller
P83C654IFB 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CMOS single-chip 8-bit microcontroller
P83C654IFBB 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CMOS single-chip 8-bit microcontroller
P83C654IFP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CMOS single-chip 8-bit microcontroller
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