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參數(shù)資料
| 型號(hào)： | P83C654IBBB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS single-chip 8-bit microcontroller |
| 中文描述： | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 X 1.75 MM, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 66/88頁 |
| 文件大小： | 497K |
| 代理商： | P83C654IBBB |
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Philips Semiconductors
Product data
P83C654X2/P87C654X2
80C51 8-bit microcontroller family
16 kB OTP/ROM,
256B RAM, low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz)
2004 Apr 20
66
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0
°
C to +70
°
C or –40
°
C to +85
°
C;
V
CC
= 2.7 V to 5.5 V
; V
SS
= 0 V (16 MHz max. CPU clock)
SYMBOL
PARAMETER
TEST
CONDITIONS
LIMITS
UNIT
MIN
TYP
1
MAX
V
IL
Input LOW voltage
11
, except P1.6 and P1.7
4.0 V < V
CC
< 5.5 V
2.7 V < V
CC
< 4.0 V
–0.5
–0.5
–0.5
–0.5
0.2V
CC
+ 0.9
0.7V
CC
–
0.2V
CC
– 0.1
0.7V
CC
0.2V
DD
– 0.3
0.3V
DD
V
CC
+ 0.5
V
CC
+ 0.5
0.4
V
V
V
V
V
V
V
V
IL1
V
IL2
V
IH
V
IH1
V
OL
Input LOW voltage to EA
Input LOW voltage to P1.6/SCL, P1.7/SDA
5
Input HIGH voltage (ports 0, 1, 2, 3, EA)
Input HIGH voltage, XTAL1, RST
11
Output LOW voltage, ports 1, 2
8
, except P1.6
and P1.7
Output LOW voltage, port 0, ALE, PSEN
8, 7
Output LOW voltage, P1.6/SCL, P1.7/SDA
Output HIGH voltage, ports 1, 2, 3
3
V
CC
= 2.7 V; I
OL
= 1.6 mA
2
V
OL1
V
OL2
V
OH
V
CC
= 2.7 V; I
OL
= 3.2 mA
2
IOL
= 3.0 mA
7
V
CC
= 2.7 V; I
OH
= –20 A
V
CC
= 4.5 V; I
OH
= –30 A
V
CC
= 2.7 V; I
OH
= –3.2 mA
–
–
V
CC
– 0.7
V
CC
– 0.7
V
CC
– 0.7
0.4
0.4
–
–
–
V
V
V
V
V
V
OH1
Output HIGH voltage (port 0 in external bus
mode), ALE
9
, PSEN
3
Logical 0 input current, ports 1, 2, 3
Logical 1-to-0 transition current, ports 1, 2, 3
6
Input leakage current, port 0
Power supply current (see Figure 49 and
Source Code):
Active mode @ 16 MHz
I
IL
I
TL
I
LI
I
CC
V
IN
= 0.4 V
V
IN
= 2.0 V; See note 4
0.45 < V
IN
< V
CC
– 0.3
–1
–
–
–50
–650
±
10
A
A
A
A
Idle mode @ 16 MHz
A
Power-down mode or clock stopped
(see Figure 45 for conditions)
12
T
amb
= 0
°
C to 70
°
C
2
30
A
T
amb
= –40
°
C to +85
°
C
3
50
A
V
RAM
R
RST
C
IO
RAM keep-alive voltage
Internal reset pull-down resistor
Pin capacitance
10
(except EA)
1.2
40
–
V
k
pF
225
15
NOTES:
1. Typical ratings are not guaranteed. Values listed are based on tests conducted on limited number of samples at room temperature.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
OL
s of ALE and ports 1 and 3. The noise is
due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations.
In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to
qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
OL
can exceed these conditions provided
that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the V
OH
on ALE and PSEN to momentarily fall below the V
CC
–0.7 specification when the
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V
IN
is approximately 2 V.
5. See Figures 51 through 54 for I
CC
test conditions and Figure 49 for I
CC
vs. Frequency
12-clock mode characteristics:
Active mode (operating):
I
CC
= 1.0 mA + 1.1 mA
×
FREQ.[MHz]
Active mode (reset):
I
CC
= 7.0 mA + 0.6 mA
FREQ.[MHz]
Idle mode:
I
CC
= 1.0 mA + 0.22 mA
FREQ.[MHz]
6. This value applies to T
amb
= 0
°
C to +70
°
C. For T
amb
= –40
°
C to +85
°
C, I
TL
= –750 A.
7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
8. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin:
15 mA (*NOTE: This is 85
°
C specification.)
Maximum I
per 8-bit port:
26 mA
Maximum total I
for all outputs:
71 mA
If I
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
9. ALE is tested to V
OH1
, except when ALE is off then V
OH
is the voltage specification.
10.Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF
(except EA is 25 pF).
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