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參數(shù)資料
| 型號： | P83C654EHP |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | CMOS single-chip 8-bit microcontroller |
| 中文描述： | CMOS單芯片8位微控制器 |
| 文件頁數(shù)： | 79/88頁 |
| 文件大小： | 497K |
| 代理商： | P83C654EHP |
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Philips Semiconductors
Product data
P83C654X2/P87C654X2
80C51 8-bit microcontroller family
16 kB OTP/ROM,
256B RAM, low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz)
2004 Apr 20
79
EPROM CHARACTERISTICS
The 87C654X2 can be programmed by using a modified Improved
Quick-Pulse Programming
algorithm. It differs from older methods
in the value used for V
PP
(programming supply voltage) and in the
width and number of the ALE/PROG pulses.
The family contains two signature bytes that can be read and used
by an EPROM programming system to identify the device. The
signature bytes identify the device as being manufactured by
Philips.
Table 15 shows the logic levels for reading the signature byte, and
for programming the program memory, the encryption table, and the
security bits. The circuit configuration and waveforms for quick-pulse
programming are shown in Figures 55 and 56. Figure 57 shows the
circuit configuration for normal program memory verification.
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in
Figure 55. Note that the device is running with a 4 to 6MHz
oscillator. The reason the oscillator needs to be running is that the
device is executing internal address and program data transfers.
The address of the EPROM location to be programmed is applied to
ports 1 and 2, as shown in Figure 55. The code byte to be
programmed into that location is applied to port 0. RST, PSEN and
pins of ports 2 and 3 specified in Table 15 are held at the ‘Program
Code Data’ levels indicated in Table 15. The ALE/PROG is pulsed
LOW 5 times as shown in Figure 56.
To program the encryption table, repeat the 5 pulse programming
sequence for addresses 0 through 1FH, using the ‘Pgm Encryption
Table’ levels. Do not forget that after the encryption table is
programmed, verification cycles will produce only encrypted data.
To program the security bits, repeat the 5 pulse programming
sequence using the ‘Pgm Security Bit’ levels. After one security bit is
programmed, further programming of the code memory and
encryption table is disabled. However, the other security bits can still
be programmed.
Note that the EA/V
PP
pin must not be allowed to go above the
maximum specified V
PP
level for any amount of time. Even a narrow
glitch above that voltage can cause permanent damage to the
device. The V
PP
source should be well regulated and free of glitches
and overshoot.
Program Verification
If security bits 2 and 3 have not been programmed, the on-chip
program memory can be read out for program verification. The
address of the program memory locations to be read is applied to
ports 1 and 2 as shown in Figure 57. The other pins are held at the
‘Verify Code Data’ levels indicated in Table 15. The contents of the
address location will be emitted on port 0. External pull-ups are
required on port 0 for this operation.
If the 64 byte encryption table has been programmed, the data
presented at port 0 will be the exclusive NOR of the program byte
with one of the encryption bytes. The user will have to know the
encryption table contents in order to correctly decode the verification
data. The encryption table itself cannot be read out.
Reading the Signature Bytes
The signature bytes are read by the same procedure as a normal
verification of locations 030H and 031H, except that P3.6 and P3.7
need to be pulled to a logic LOW. The values are:
(030H) = 15H indicates manufactured by Philips
(031H) = 99H
(060H) = 02H
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 15,
and which satisfies the timing specifications, is suitable.
Security Bits
With none of the security bits programmed the code in the program
memory can be verified. If the encryption table is programmed, the
code will be encrypted when verified. When only security bit 1 (see
Table 16) is programmed, MOVC instructions executed from
external program memory are disabled from fetching code bytes
from the internal memory, EA is latched on Reset and all further
programming of the EPROM is disabled. When security bits 1 and 2
are programmed, in addition to the above, verify mode is disabled.
When all three security bits are programmed, all of the conditions
above apply and all external program memory execution is disabled.
Encryption Array
64 bytes of encryption array are initially unprogrammed (all 1s).
Trademark phrase of Intel Corporation.
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