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參數(shù)資料
| 型號(hào)： | P83C654EFBB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS single-chip 8-bit microcontroller |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 X 1.75 MM, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 71/88頁 |
| 文件大?。?/td> | 497K |
| 代理商： | P83C654EFBB |
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Philips Semiconductors
Product data
P83C654X2/P87C654X2
80C51 8-bit microcontroller family
16 kB OTP/ROM,
256B RAM, low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz)
2004 Apr 20
71
AC ELECTRICAL CHARACTERISTICS (6-CLOCK MODE, 5 V
±
10 % OPERATION)
T
amb
= 0
°
C to +70
°
C or –40
°
C to +85
°
C; V
CC
= 5 V
±
10 %, V
SS
= 0 V
1,2,3,4,5
Symbol
Figure
Parameter
Limits
MIN
16 MHz Clock
MIN
Unit
MAX
MAX
1/t
CLCL
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
Data Memory
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
WHQX
t
QVWH
t
RLAZ
t
WHLH
External Clock
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Shift register
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
46
41
41
41
41
41
41
41
41
41
41
41
Oscillator frequency
ALE pulse width
Address valid to ALE LOW
Address hold after ALE LOW
ALE LOW to valid instruction in
ALE LOW to PSEN LOW
PSEN pulse width
PSEN LOW to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN LOW to address float
0
t
CLCL
– 8
0.5t
CLCL
– 13
0.5t
CLCL
– 20
–
0.5t
CLCL
– 10
1.5t
CLCL
– 10
–
0
–
–
–
30
–
–
–
2t
CLCL
–35
–
–
1.5t
CLCL
– 35
–
0.5t
CLCL
– 10
2.5t
CLCL
– 35
10
–
54.5
18.25
11.25
–
21.25
83.75
–
0
–
–
–
–
–
–
–
90
–
–
58.75
–
21.25
121.25
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
42
43
42
42
42
42
42
42, 43
42, 43
43
43
43
42
42, 43
RD pulse width
WR pulse width
RD LOW to valid data in
Data hold after RD
Data float after RD
ALE LOW to valid data in
Address to valid data in
ALE LOW to RD or WR LOW
Address valid to WR LOW or RD LOW
Data valid to WR transition
Data hold after WR
Data valid to WR HIGH
RD LOW to address float
RD or WR HIGH to ALE HIGH
3t
CLCL
– 20
3t
CLCL
– 20
–
0
–
–
–
1.5t
CLCL
– 15
2t
CLCL
–15
0.5t
CLCL
– 25
0.5t
CLCL
– 15
3.5t
CLCL
– 5
–
0.5t
CLCL
– 10
–
–
2.5t
CLCL
– 35
–
t
CLCL
–10
4t
CLCL
– 35
4.5t
CLCL
– 35
1.5t
CLCL
+15
–
–
–
–
0
0.5t
CLCL
+10
167.5
167.5
–
0
–
–
–
78.75
110
6.25
16.25
213.75
–
21.25
–
–
121.25
–
52.5
215
246.25
108.75
–
–
–
–
0
41.25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
46
46
46
46
High time
Low time
Rise time
Fall time
0.4t
CLCL
0.4t
CLCL
–
–
t
CLCL
– t
CLCX
t
CLCL
– t
CHCX
5
5
–
–
–
–
–
–
–
–
ns
ns
ns
ns
45
45
45
45
45
Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
6
6t
CLCL
5t
CLCL
–25
t
CLCL
– 15
0
–
–
–
–
–
5t
CLCL
– 133
375
287.5
47.5
0
–
–
–
–
–
179.5
ns
ns
ns
ns
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN=100 pF, load capacitance for all outputs = 80 pF
3. Interfacing the microcontroller to devices with float time up to 45ns is permitted. This limited bus contention will not cause damage to port 0
drivers.
4. Parts are guaranteed by design to operate down to 0 Hz.
5. Data shown in the table are the best mathematical models for the set of measured values obtained in tests. If a particular parameter
calculated at a customer specified frequency has a negative value, it should be considered equal to zero.
6. Below 16 MHz this parameter is 4t
CLCL
– 133
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