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參數(shù)資料
| 型號： | P83C652IFPN |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS single-chip 8-bit microcontrollers |
| 中文描述： | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, PLASTIC, SOT-129-1, DIP-40 |
| 文件頁數(shù)： | 12/22頁 |
| 文件大?。?/td> | 185K |
| 代理商： | P83C652IFPN |
Phlips Semiconductors
Product specification
80C652/83C652
CMOS single-chip 8-bit microcontrollers
1997 Dec 05
12
AC ELECTRICAL CHARACTERISTICS
1, 2
(16 MHz type)
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1/t
CLCL
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
Data Memory
2
Oscillator frequency
3.5
16
MHz
2
ALE pulse width
85
2t
CLCL
–40
t
CLCL
–55
t
CLCL
–35
ns
2
Address valid to ALE low
8
ns
2
Address hold after ALE low
28
ns
2
ALE low to valid instruction in
150
4t
CLCL
–100
ns
2
ALE low to PSEN low
23
t
CLCL
–40
3t
CLCL
–45
ns
2
PSEN pulse width
143
ns
2
PSEN low to valid instruction in
83
3t
CLCL
–105
ns
2
Input instruction hold after PSEN
0
0
ns
2
Input instruction float after PSEN
38
t
CLCL
–25
5t
CLCL
–105
10
ns
2
Address to valid instruction in
208
ns
2
PSEN low to address float
10
ns
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
DW
t
WHQX
t
RLAZ
t
WHLH
Shift Register
3, 4
RD pulse width
275
6t
CLCL
–100
6t
CLCL
–100
ns
3, 4
WR pulse width
275
ns
3, 4
RD low to valid data in
148
5t
CLCL
–165
ns
3, 4
Data hold after RD
0
0
ns
3, 4
Data float after RD
55
2t
CLCL
–70
8t
CLCL
–150
9t
CLCL
–165
3t
CLCL
+50
ns
3, 4
ALE low to valid data in
350
ns
3, 4
Address to valid data in
398
ns
3, 4
ALE low to RD or WR low
138
238
3t
CLCL
–50
4t
CLCL
–130
t
CLCL
–60
7t
CLCL
–150
t
CLCL
–50
ns
3, 4
Address valid to WR low or RD low
120
ns
3, 4
Data valid to WR transition
3
ns
3, 4
Data setup time before WR
288
ns
3, 4
Data hold after WR
13
ns
3, 4
RD low to address float
0
0
ns
3, 4
RD or WR high to ALE high
23
103
t
CLCL
–40
t
CLCL
+40
ns
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
External Clock
5
Serial port clock cycle time
3
Output data setup to clock rising edge
3
Output data hold after clock rising edge
3
Input data hold after clock rising edge
3
Clock rising edge to input data valid
3
0.75
12t
CLCL
10t
CLCL
–133
2t
CLCL
–117
0
μ
s
ns
5
492
5
80
ns
5
0
ns
5
492
10t
CLCL
–133
ns
t
CHCX
t
CLCX
t
CLCH
t
CHCL
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. These values are characterized but not 100% production tested.
6
High time
3
Low time
3
Rise time
3
Fall time
3
20
20
t
CLCL –
t
CLCX
t
CLCL –
t
CHCX
20
ns
6
20
20
ns
6
20
ns
6
20
20
ns
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相關代理商/技術參數(shù) |
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| P83C654EBA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CMOS single-chip 8-bit microcontroller |
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