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    參數(shù)資料
    型號(hào): P83C652FFB
    廠商: NXP SEMICONDUCTORS
    元件分類: 微控制器/微處理器
    英文描述: CMOS single-chip 8-bit microcontrollers
    中文描述: 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44
    文件頁(yè)數(shù): 14/22頁(yè)
    文件大?。?/td> 185K
    代理商: P83C652FFB
    Phlips Semiconductors
    Product specification
    80C652/83C652
    CMOS single-chip 8-bit microcontrollers
    1997 Dec 05
    14
    AC ELECTRICAL CHARACTERISTICS – I
    2
    C INTERFACE
    SYMBOL
    PARAMETER
    INPUT
    OUTPUT
    SCL TIMING CHARACTERISTICS
    t
    HD;STA
    START condition hold time
    t
    LOW
    SCL LOW time
    t
    HIGH
    SCL HIGH time
    t
    RC
    SCL rise time
    t
    FC
    SCL fall time
    SDA TIMING CHARACTERISTICS
    t
    SU;DAT1
    Data set-up time
    t
    SU;DAT2
    SDA set-up time (before rep. START cond.)
    t
    SU;DAT3
    SDA set-up time (before STOP cond.)
    t
    HD;DAT
    Data hold time
    t
    SU;STA
    Repeated START set-up time
    t
    SU;STO
    STOP condition set-up time
    t
    BUF
    Bus free time
    t
    RD
    SDA rise time
    t
    FD
    SDA fall time
    NOTES:
    1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
    2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1
    μ
    s.
    3. Spikes on the SDA and SCL lines with a duration of less than 3 t
    CLCL
    will be filtered out. Maximum capacitance on bus-lines SDA and
    SCL = 400pF.
    4. t
    CLCL
    = 1/f
    OSC
    = one oscillator clock period at pin XTAL1. For 63ns (42ns) < t
    CLCL
    < 285ns (16MHz (24MHz) > f
    OSC
    > 3.5MHz) the SI01
    interface meets the I
    2
    C-bus specification for bit-rates up to 100 kbit/s.
    14 t
    CLCL
    16 t
    CLCL
    14 t
    CLCL
    1
    μ
    s
    > 4.0
    μ
    s
    1
    > 4.7
    μ
    s
    1
    > 4.0
    μ
    s
    1
    2
    < 0.3
    μ
    s
    3
    0.3
    μ
    s
    250ns
    > 20 t
    CLCL
    – t
    RD
    > 1
    μ
    s
    1
    > 8 t
    CLCL
    > 8 t
    CLCL
    – t
    FC
    > 4.7
    μ
    s
    1
    > 4.0
    μ
    s
    1
    > 4.7
    μ
    s
    1
    2
    < 0.3
    μ
    s
    3
    250ns
    250ns
    0ns
    14 t
    CLCL
    14 t
    CLCL
    14 t
    CLCL
    1
    μ
    s
    0.3
    μ
    s
    TIMING SIO1 (I
    2
    C) INTERFACE
    t
    RD
    t
    SU;STA
    t
    BUF
    t
    SU; STO
    0.7 V
    DD
    0.3 V
    DD
    0.7 V
    DD
    0.3 V
    DD
    t
    FD
    t
    RC
    t
    FC
    t
    HIGH
    t
    LOW
    t
    HD;STA
    t
    SU;DAT1
    t
    HD;DAT
    t
    SU;DAT2
    t
    SU;DAT3
    START condition
    repeated START condition
    SDA
    (INPUT/OUTPUT)
    SCL
    (INPUT/OUTPUT)
    STOP condition
    START or repeated START condition
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    參數(shù)描述
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