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參數(shù)資料
| 型號： | P83C592FHA |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-bit microcontroller with on-chip CAN |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, SOT-168-3, MO-047AE, LCC-68 |
| 文件頁數(shù)： | 52/108頁 |
| 文件大?。?/td> | 650K |
| 代理商： | P83C592FHA |
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1996 Jun 27
52
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xC592
handbook, full pagewidth
MGA163
tSYNCSEG
sample point
(b)
1 clock cycle (t
)
SCL
tTSEG1
tTSEG2
t(one bit period)
SYNC.SEG
sample point
(a)
nominal bit time
PROP.SEG
PHASE SEG1
PHASE SEG2
transmit point
Fig.18 Bit period.
(a) As defined by the CAN-protocol.
(b) As implemented in the P8xC592's on-chip CAN-controller.
13.5.19.2 Time Segment 1 (TSEG1)
This segment determines the location of the sampling
point within a bit period, which is at the end of TSEG1.
TSEG1 is programmable from 1 to 16 system clock cycles
(see Section 13.5.10).
The correct location of the sample point is essential for the
correct functioning of a transmission. The following points
must be taken into consideration:
A Start-Of-Frame (see Section 13.6.2) causes all
CAN-controllers to perform a ‘hard synchronization’
(see Section 13.5.20) on the first recessive-to-dominant
edge.
During arbitration, however, several CAN-controllers
may simultaneously transmit. Therefore it may require
twice the sum of bus-line, input comparator and the
output driver delay times until the bus is stable.
This is the propagation delay time.
To avoid sampling at an incorrect position, it is
necessary to include an additional synchronization
buffer on both sides of the sample point.
The main reasons for incorrect sampling are:
– Incorrect synchronization due to spikes on the
bus-line
– Slight variations in the oscillator frequency of each
CAN-controller in the network, which results in a
phase error.
Time Segment 1 consists of the segment for
compensation of propagation delays and the
synchronization buffer segment directly before the
sample point (see Fig.18).
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