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參數(shù)資料
| 型號： | P83C552KBB |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Single-chip 8-bit microcontroller |
| 中文描述： | 單芯片8位微控制器 |
| 文件頁數(shù)： | 20/23頁 |
| 文件大?。?/td> | 185K |
| 代理商： | P83C552KBB |
Philips Semiconductors
Product data
80C552/83C552
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
2002 Sep 03
20
SU01704
V
DD
P0
EA
EW
RST
XTAL1
XTAL2
V
SS
V
DD
V
DD
V
DD
I
DD
(NC)
CLOCK SIGNAL
V
DD
P1.6
P1.7
STADC
AV
SS
AV
ref–
Figure 12. I
DD
Test Condition, Active Mode
All other pins are disconnected
1
SU01705
V
DD
P0
EA
RST
XTAL1
XTAL2
V
SS
V
DD
V
DD
I
DD
(NC)
CLOCK SIGNAL
V
DD
P1.6
P1.7
STADC
EW
AV
SS
AV
ref–
Figure 13. I
DD
Test Condition, Idle Mode
All other pins are disconnected
2
SU01706
V
DD
–0.5
0.5 V
0.7V
DD
0.2V
DD
–0.1
t
CHCL
t
CLCL
t
CLCH
t
CLCX
t
CHCX
Figure 14. Clock Signal Waveform for I
DD
Tests in Active and
Idle Modes t
CLCH
= t
CHCL
= 5ns
SU01707
V
DD
P0
RST
XTAL1
XTAL2
V
SS
V
DD
V
DD
I
DD
(NC)
V
DD
P1.6
P1.7
STADC
EA
EW
AV
SS
AV
ref–
Figure 15. I
DD
Test Condition, Power Down Mode
All other pins are disconnected. V
DD
= 2 V to 5.5 V
3
NOTES:
1. Active Mode:
a. The following pins must be forced to V
DD
: EA, RST, Port 0, and EW.
b. The following pins must be forced to V
SS
: STADC, AV
ss
, and AV
ref–
.
c. Ports 1.6 and 1.7 should be connected to V
DD
through resistors of sufficiently high value such that the sink current into these pins cannot
exceed the I
OL1
spec of these pins.
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
2. Idle Mode:
a. The following pins must be forced to V
DD
: Port 0 and EW.
b. The following pins must be forced to V
SS
: RST, STADC, AV
ss
,, AV
ref–
, and EA.
c. Ports 1.6 and 1.7 should be connected to V
DD
through resistors of sufficiently high value such that the sink current into these pins cannot
exceed the I
OL1
spec of these pins. These pins must not have logic 0 written to them prior to this measurement.
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
3. Power Down Mode:
a. The following pins must be forced to V
DD
: Port 0 and EW.
b. The following pins must be forced to V
SS
: RST, STADC, XTAL1, AV
ss
,, AV
ref–
, and EA.
c. Ports 1.6 and 1.7 should be connected to V
DD
through resistors of sufficiently high value such that the sink current into these pins cannot
exceed the I
OL1
spec of these pins. These pins must not have logic 0 written to them prior to this measurement.
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
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