參數(shù)資料
型號: P83C524IBP
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-bit microcontrollers
中文描述: 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP40
封裝: 0.600 INCH, PLASTIC, DIP-40
文件頁數(shù): 34/76頁
文件大?。?/td> 400K
代理商: P83C524IBP
1997 Dec 15
34
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
13.1
I
2
C Interrupt Register (S1INT)
Table 15
I
2
C Interrupt register (address DAH)
(1)
Note
1.
SI bit
: writing a logic 0 clears this bit, writing a logic 1 has no effect.
Table 16
Description of the S1INT bits
13.2
Single-bit Data Register with I
2
C Auto-clock (S1BIT)
Table 17
Single-bit Data register with I
2
C Auto-clock (address D9H)
(1)
Note
1.
Access of the
S1BIT SFR
clears SI, CLH, RBF and WBF. It starts the auto-clock if SCO = 0.
Table 18
Description of the S1BIT bits
7
6
5
4
3
2
1
0
SI
X
X
X
X
X
X
X
BIT
SYMBOL
FUNCTION
7
SI
Serial Interrupt request (SI) flag
: if a START condition occurs the SI flag in the S1INT
SFR is set on the falling edge of the filtered serial clock. If SI = 1 is detected during a
transfer this can be a 'spurious START' error condition. If no transfer is taking place the
SI = 1 is a START from an external master. Provided the bits EA and ES1 in IE SFR are
set, SI then generates an interrupt so that a slave address receive routine can be
started. SI can be cleared by accessing the S1BIT register or by writing '00' to S1INT.
Also after reception of a START condition, the LOW period of the clock pulse is
stretched, suspending the serial transfer to allow the software to take action. This clock
stretching is ended by a read or write access to S1BIT.
X = undefined during read, don't care during write.
6 to 0
7
6
5
4
3
2
1
0
READ
SDI
0
0
0
0
0
0
0
WRITE
SDO
X
X
X
X
X
X
X
BIT
SYMBOL
FUNCTION
7
SDO/SDI
Serial Data Output (SDO) and the filtered Serial Data Input (SDI)
. SDI data is latched
on the rising edge of the filtered serial clock. S1BIT.7 accesses the same memory
locations as S1SCS.7. S1BIT SFR is not bit-addressable.
X = don't care.
6 to 0
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