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    參數(shù)資料
    型號(hào): P83C51FC-5N
    廠商: NXP SEMICONDUCTORS
    元件分類: 微控制器/微處理器
    英文描述: 80C51 8-bit microcontroller family 8K.64K/256.1K OTP/ROM/ROMless, low voltage 2.7V.5.5V, low power, high speed 33 MHz
    中文描述: 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP40
    封裝: 0.600 INCH, PLASTIC, MO-015, SOT-129-1, DIP-40
    文件頁數(shù): 24/56頁
    文件大?。?/td> 337K
    代理商: P83C51FC-5N
    Philips Semiconductors
    Product specification
    8XC52/54/58/80C32
    8XC51FA/FB/FC/80C51FA
    8XC51RA+/RB+/RC+/RD+/80C51RA+
    80C51 8-bit microcontroller family
    8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
    low power, high speed (33MHz)
    1999 Apr 01
    24
    Reduced EMI Mode
    The AO bit (AUXR.0) in the AUXR register when set disables the
    ALE output.
    Reduced EMI Mode
    AUXR (8EH)
    7
    6
    5
    4
    3
    2
    1
    0
    EXTRAM
    AO
    AUXR.1
    AUXR.0
    EXTRAM
    AO
    (RX+ only)
    Turns off ALE output.
    Dual DPTR
    The dual DPTR structure (see Figure 13) is a way by which the chip
    will specify the address of an external data memory location. There
    are two 16-bit DPTR registers that address the external memory,
    and a single bit called DPS = AUXR1/bit0 that allows the program
    code to switch between them.
    New Register Name: AUXR1#
    SFR Address: A2H
    Reset Value: xxxx00x0B
    7
    6
    5
    4
    3
    2
    1
    0
    LPEP
    GF3
    0
    DPS
    Where:
    DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.
    Select Reg
    DPS
    DPTR0
    DPTR1
    0
    1
    The DPS bit status should be saved by software when switching
    between DPTR0 and DPTR1.
    The GF3 bit is a general purpose user–defined flag. Note that bit 2 is
    not writable and is always read as a zero. This allows the DPS bit to
    be quickly toggled simply by executing an INC DPTR instruction
    without affecting the GF3 or LPEP bits.
    DPS
    DPTR1
    DPTR0
    DPH
    (83H)
    DPL
    (82H)
    EXTERNAL
    DATA
    MEMORY
    SU00745A
    BIT0
    AUXR1
    Figure 13.
    DPTR Instructions
    The instructions that refer to DPTR refer to the data pointer that is
    currently selected using the AUXR1/bit 0 register. The six
    instructions that use the DPTR are as follows:
    INC DPTR
    Increments the data pointer by 1
    MOV DPTR, #data16
    Loads the DPTR with a 16-bit constant
    MOV A, @ A+DPTR
    Move code byte relative to DPTR to ACC
    MOVX A, @ DPTR
    Move external RAM (16-bit address) to
    ACC
    MOVX @ DPTR , A
    Move ACC to external RAM (16-bit
    address)
    JMP @ A + DPTR
    Jump indirect relative to DPTR
    The data pointer can be accessed on a byte-by-byte basis by
    specifying the low or high byte in an instruction which accesses the
    SFRs. See application note AN458 for more details.
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    參數(shù)描述
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    P83C51FC-IB 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit CMOS (low voltage, low power and high speed) microcontroller families
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