參數(shù)資料
型號(hào)： P83C434
廠商： NXP Semiconductors N.V.
英文描述： 8-bit microcontrollers with LCD-driver
中文描述： 8位微控制器與LCD驅(qū)動(dòng)器
文件頁(yè)數(shù)： 13/36頁(yè)
文件大?。?/td> 165K
代理商： P83C434
1997 Jul 03
13
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
P83C434; P83C834
6.3.2
P
RIORITY LEVEL STRUCTURE
The priority level of each interrupt source can be
individually programmed by setting or clearing a bit in the
Interrupt Priority Register (IP; see Section 6.3.4). A low
priority interrupt can itself be interrupted by a high priority
interrupt, but not by another low priority interrupt. A high
priority interrupt can not be interrupted by another interrupt
source.
If two requests of different priority levels are received
simultaneously, the request of higher priority level is
serviced. If request of the same priority level is received
simultaneously, an internal polling sequence determines
which request is serviced. Thus, within each priority level
there is a second priority structure determined as shown in
Table 6.
The IP register contains a number of not implemented bits.
IP.7, IP.6 and IP.5 are reserved in the 80C51.
User software should not write logic 1’s to these positions,
since they may be used in other 8051-Family products.
Table 6
Priority within levels
Note
1.
The ‘Priority within level’ structure is only used to
resolve simultaneous requests of the same priority
level.
6.3.3
H
OW
I
NTERRUPTS ARE HANDLED
The interrupt flags are sampled at S5P2 of every machine
cycle. The samples are polled during the following
machine cycle. If one of the flags was in a set condition at
S5P2 of the preceding cycle, the polling cycle will find it
and the interrupt system will generate an LCALL to the
appropriate service routine, provided this hardware
generated LCALL is not blocked by any of the following
conditions:
1.
An interrupt of equal priority or higher priority level is
already in progress.
2.
The current (polling) cycle is not the final cycle in the
execution of the instruction in progress.
3.
The instruction in progress is RETI or any write to the
IE or IP registers.
SOURCE
IE0
′
TF0
IE1
′
TF1
PRIORITY WITHIN LEVEL
(1)
1 (highest)
2
3
4 (lowest)
Condition 2 ensures that the instruction in progress will be
completed before vectoring to any service routine.
Condition 3 ensures that if the instruction in progress is
RETI or any access to IE or IP, then at least one more
instruction will be executed before the interrupt is vectored
to.
The polling cycle is repeated with each machine cycle, and
the values polled are the values that were present at S5P2
of the previous machine cycle. Note that if an interrupt flag
is active but not being responded to for one of the above
mentioned conditions, if the flag is still inactive when the
blocking condition is removed, the denied interrupt will not
be serviced. In other words, the fact that the interrupt flag
was once active but not serviced is not remembered.
Every polling cycle is new.
The polling cycle/LCALL sequence is illustrated in
“Data Handbook IC20, 80C51 Family, Fig.20”
Note that if an interrupt of higher priority level becomes
active prior to S5P2 of the machine cycle labelled C3
(“Data Handbook IC20, 80C51 Family, Fig.20”) then in
accordance with the above rules it will be vectored to
during C5 and C6, without any instruction of the lower
priority routine having been executed. Thus the processor
acknowledges an interrupt request by executing a
hardware generated LCALL to the appropriate servicing
routine. The hardware generated LCALL pushes the
contents of the Program Counter on to the stack (but it
does not save the PSW) and reloads the PC with an
address that depends on the source of the interrupt being
vectored to as shown in Table 7.
Execution proceeds from that location until the RETI
instruction is encountered. The RETI instruction informs
the processor that the interrupt routine is no longer in
progress, then pops the top two bytes from the stack and
reloads the Program Counter. Execution of the interrupted
program continues from where it left off.
Note that a simple RET instruction would also return
execution to the interrupted program, but it would have left
the interrupt control system thinking an interrupt was still in
progress, making future interrupts impossible.
Table 7
Vector addresses
SOURCE
IE0
′
TF0
IE1
′
TF1
VECTOR ADDRESS
0003H
000BH
0013H
001BH
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