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參數(shù)資料
| 型號： | P83C251TQ24 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 8/36頁 |
| 文件大?。?/td> | 813K |
| 代理商： | P83C251TQ24 |
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8xC251TB/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
10
VSS2
GND
Secondary Ground 2. This ground is provided to reduce ground bounce
and improve power supply bypassing. Connection of this pin to ground is
recommended. However, when using the 8xC251TB/TQ as a pin-for-pin
replacement for the 8XC51FX, VSS2 can be unconnected without loss of
compatibility. (Not available on DIP)
—
WAIT#
I
Real-time Wait State Input. The real-time WAIT# input is enabled by
writing a logical ‘1’ to the WCON.0 (RTWE) bit at S:A7H. During bus
cycles, the external memory system can signal ‘system ready’ to the
microcontroller in real time by controlling the WAIT# input signal on the
port 1.6 input.
P1.6/CEX3
WCLK
O
Wait Clock Output. The real-time WCLK output is driven at port 1.7
(WCLK) by writing a logical ‘1’ to the WCON.1 (RTWCE) bit at S:A7H.
When enabled, the WCLK output produces a square wave signal with a
period of one-half the oscillator frequency.
P1.7/CEX4/
A17
WR#
O
Write. Write signal output to external memory.
P3.6
XTAL1
I
Input to the On-chip, Inverting, Oscillator Amplifier. To use the
internal oscillator, a crystal/resonator circuit is connected to this pin. If an
external oscillator is used, its output is connected to this pin. XTAL1 is the
clock source for internal timing.
—
XTAL2
O
Output of the On-chip, Inverting, Oscillator Amplifier. To use the
internal oscillator, a crystal/resonator circuit is connected to this pin. If an
external oscillator is used, leave XTAL2 unconnected.
—
NOTE:
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (compatible with 44-pin
PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page-mode operation, port 0 carries the lower
address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0).
Table 7. Memory Signal Selections (RD1:0)
RD1:0
P1.7/CEX/
A17/WCLK
P3.7/RD#/A16
PSEN#
WR#
Features
0 0
A17
A16
Asserted for all
addresses
Asserted for writes to
all memory locations
256-Kbyte external
memory
0 1
P1.7/CEX4/
WCLK
A16
Asserted for all
addresses
Asserted for writes to
all memory locations
128-Kbyte external
memory
1 0
P1.7/CEX4/
WCLK
P3.7 only
Asserted for all
addresses
Asserted for writes to
all memory locations
64-Kbyte external
memory. One
additional port pin.
1 1
P1.7/CEX4/
WCLK
RD# asserted
for addresses
≤ 7F:FFFFH
Asserted for
≥ 80:0000H
Asserted only for
writes to MCS 51
microcontroller data
memory locations.
64-Kbyte external
memory. Compatible
with MCS 51 micro-
controllers.
Table 6. Signal Descriptions (Sheet 3 of 3)
Signal
Name
Type
Description
Alternate
Function
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