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參數(shù)資料
| 型號： | P83C145BBP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICRO 21 F SOD |
| 中文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42 |
| 文件頁數(shù)： | 22/40頁 |
| 文件大?。?/td> | 243K |
| 代理商： | P83C145BBP |
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1996 Mar 22
22
Philips Semiconductors
Product specification
Microcontrollers for TV and video (MTV)
83C145; 83C845
83C055; 87C055
13.7
OSD Control Register OSCON
Table 23
OSD Control Register OSCON (address C0H)
Table 24
Description of OSCON bits (see note 1)
Note
1.
It is theoretically possible that a VSYNC interrupt could be missed, or an extra one generated, if OSCON is read,
then modified internally (e.g. in ACC), and the result written back to OSCON. However, none of the other bits in
OSCON are reasonable candidates for dynamic change. Special provisions are included in the 83C055 logic so that
IV will not be changed by a single ‘read-modify-write’ instruction such as SETB or CLR, unless the instruction
specifically changes IV.
7
6
5
4
3
2
1
0
IV
Pv
Lv
Ph
Pc
Po
DH
BFe
BIT
SYMBOL
DESCRIPTION
7
IV
Interrupt flag for the OSD feature. Bit IV is set by the leading edge of the VSYNC pulse,
and is cleared by the hardware when the VSYNC interrupt routine is vectored to. It can
also be set or cleared by software writing a logic 1 or logic 0 to this bit.
Pv defines the active VSYNC input polarity. If Pv = 0, then VSYNC input is active HIGH;
if Pv = 1, then VSYNC input is active LOW.
One effect of bit Pv is that the VID2 to VID0 and VCTRL outputs are blocked (held at
black/inactive) during the active time of VSYNC. The IV bit is set on the leading edge of
the VSYNC pulse; thus Pv controls whether the OSD interrupt occurs in response to a
HIGH-to-LOW or LOW-to-HIGH transition on VSYNC.
Lv defines the active edge of VSYNC. The active edge (leading or trailing) of VSYNC
(as defined by Pv), clears the state counter which determines the vertical start of on
screen data. Time reference for the video field is the leading edge of VSYNC, if Lv = 0,
or the trailing edge of VSYNC, if Lv = 1.
Ph defines the active HSYNC input polarity. If Ph = 0, then HSYNC input is active HIGH;
if Ph = 1, then HSYNC input is active LOW.
Pc defines the active VCTRL output polarity; VCTRL output active means: show the
colour on VID2 to VID0. If Pc = 0, then VCTRL output is active HIGH; If Pc = 1, then
VCTRL output is active LOW.
Po defines the VID2 to VID0 outputs polarity; bit is needed only because the Shadowing
feature needs to generate black pixels without reference to a register value. Internally,
the 3-bit code ‘000B’ always designates black.
If Po = 0, a logic 0 internal to the 83C055 corresponds to a LOW on one of the
VID2 to VID0 pins.
If Po = 1, a logic 1 internal to the 83C055 corresponds to a LOW on one of the
VID2 to VID0 pins.
If DH = 1, character sizes are doubled vertically but not horizontally. This feature allows
the 83C055 to be used in ‘improved definition’ systems that are not interlaced.
The vertical doubling imposed by DH does not affect the VStart logic as described in
Table 30; it operates in HSync units regardless of DH or D.
Background/Foreground enable; output BF. If BFe = 1, then the BF output tracks
whether each bit in displayed characters is a Foreground bit (LOW), or a Background bit
(HIGH). If BFe = 0, then the BF pin remains HIGH.
6
Pv
5
Lv
4
Ph
3
Pc
2
Po
1
DH
0
BFe
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