參數(shù)資料
型號(hào)： P83C055BBP
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Microcontrollers for TV and video MTV
中文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP42
封裝： 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42
文件頁(yè)數(shù)： 11/40頁(yè)
文件大?。?/td> 243K
代理商： P83C055BBP
1996 Mar 22
11
Philips Semiconductors
Product specification
Microcontrollers for TV and video (MTV)
83C145; 83C845
83C055; 87C055
11 14-BIT PWM DAC (TDAC)
11.1
14-bit counter
The 14-bit counter was already mentioned in Section 10.
The nature of the counter is such that it can achieve a
stable output value through its MSB, and the value can
propagate through logic like that shown in Fig.5. The logic
output can be stable within:
one period of the PWM clock (e.g. 250 ns) if
edge-triggered logic is used to capture the logic output,
or
one phase of the PWM clock (e.g. 125 ns) if a phase of
the PWM clock is used to capture the logic output.
The 14-bit (TDAC) counter is a ripple counter (cost and
die-size reasons).
The 14-bit PWM DAC is controlled by two special function
registers TDACL and TDACH.
11.2
14-bit DAC operation
When software wishes to change the 14-bit value
(TD0 to TD13), it should first write to TDACL and then
write to TDACH. Alternatively, if the required precision of
the duty cycle is satisfied by 6 bits or less, software can
simply write to TDACH (TD8 to TD13).
11.2.1
L
OW PRECISION OPERATION
Figure 5 shows that this block includes an ‘extra’ 14-bit
latch between TDACL - TDACH and the comparator and
other logic. The programmed value is clocked into the
operative latch when the 7 low-order bits of the counter roll
over to zero, provided that the software is not in the midst
of loading a new 14-bit value, i.e. it is not between writing
TDACL and writing TDACH.
In a similar fashion to the lower-precision PWMs, this
facility has an output flip-flop that is set when the lower
7 bits of the counter overflow/wrap. The more significant
7 bits of the operative latch’s programmed value are
compared for equality against the less significant 7 bits of
the counter, and the output FF is cleared when they match.
Thus this output has a fixed period of 128 PWM clock
cycles, and the duty cycle is determined by the
programmed value.
11.2.2
H
IGH PRECISION OPERATION
For the higher-precision aspect of this feature, the 7 MSBs
of the counter are used in a logic block with the 7 LSBs of
the programmed value.
The 7
th
LSB (binary value 64) of the programmed value is
ANDed with the 7
th
MSB (128) of the counter, the 6
th
LSB
of the value is ANDed with the counter’s 6
th
and 7
th
MSBs
being 10, and so on through the LSB of the programmed
value being ANDed with the counter’s 7 MSBs being
100000. Then these 7 ANDed terms are ORed. If the
result is true (logic 1) at the time the 7 LSBs of the counter
match the MSBs of the programmed value, the output is
forced high for 1 (additional) PWM clock cycle.
The result is that, if the value-64 bit of the 14-bit value is
programmed to a logic 1, every other cycle of 128 PWM
counter clocks has its duty cycle stretched by one counter
clock; if the value-32 bit is programmed to logic 1, every
4
th
cycle is stretched, and so on through, if the value-1 bit
is programmed to logic 1, one cycle out of each 128 is
stretched.
11.2.3
14-
BIT
DAC
OUTPUT
Assuming the external integrator can handle all this, the
net effect is a PWM DAC that has the period of a 7-bit
design (which makes the integrator easier and more
feasible to design) with the accuracy of a 14-bit one.
An obvious prerequisite for such precision is that the load
on the voltage must be very light, like a single op-amp or
comparator.
11.2.3.1
Note
The TDAC feature differs from the corresponding features
of predecessor parts in several ways:
1.
The 14-bit value is functionally composed of major and
minor portions of 7 bits each.
2.
The 14-bit value is programmed as a contiguous
multi-register value that can be manipulated
straight-forwardly via arithmetic instructions.
3.
As discussed for the 6-bit DACs, both of the preceding
parts had a feature whereby the PWM output could be
inverted, redundantly with complementing the 14-bit
value. This feature has been eliminated.
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