參數(shù)資料
型號(hào)： P8254
廠商： Intersil Corporation
英文描述： CMOS Programmable Interval Timer
中文描述： CMOS可編程間隔定時(shí)器
文件頁數(shù)： 2/17頁
文件大?。?/td> 142K
代理商： P8254
4-2
Functional Diagram
Ordering Information
PART NUMBERS
10MHz
CP82C54-10
IP82C54-10
CS82C54-10
IS82C54-10
CD82C54-10
ID82C54-10
MD82C54-10/B
MR82C54-10/B
TEMPERATURE
RANGE
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
0
o
C to +70
o
C
PACKAGE
PKG. NO.
E24.6
E24.6
N28.45
N28.45
F24.6
F24.6
F24.6
J28.A
F24.6
J28.A
M24.3
8MHz
12MHz
CP82C54
IP82C54
CS82C54
IS82C54
CD82C54
ID82C54
MD82C54/B
MR82C54/B
SMD # 8406501JA
SMD# 84065013A
CM82C54
CP82C54-12
IP82C54-12
CS82C54-12
IS82C54-12
CD82C54-12
ID82C54-12
MD82C54-12/B
MR82C54-12/B
8406502JA
84065023A
CM82C54-12
24 Lead PDIP
24 Lead PDIP
28 Lead PLCC
28 Lead PLCC
24 Lead CERDIP
24 Lead CERDIP
24 Lead CERDIP
28 Lead CLCC
24 Lead CERDIP
28 Lead CLCC
24 Lead SOIC
-
-
CM82C54-10
Pin Description
SYMBOL
DIP PIN
NUMBER
TYPE
DEFINITION
D7 - D0
1 - 8
I/O
DATA: Bi-directional three-state data bus lines, connected to system data bus.
CLK 0
9
I
CLOCK 0: Clock input of Counter 0.
OUT 0
10
O
OUT 0: Output of Counter 0.
GATE 0
11
I
GATE 0: Gate input of Counter 0.
GND
12
GROUND: Power supply connection.
OUT 1
13
O
OUT 1: Output of Counter 1.
GATE 1
14
I
GATE 1: Gate input of Counter 1.
CLK 1
15
I
CLOCK 1: Clock input of Counter 1.
GATE 2
16
I
GATE 2: Gate input of Counter 2.
OUT 2
17
O
OUT 2: Output of Counter 2.
CONTROL
WORD
REGISTER
READ/
WRITE
LOGIC
DATA/
BUS
BUFFER
COUNTER
2
COUNTER
1
COUNTER
0
I
INTERNAL BUS
CONTROL
LOGIC
CONTROL
WORD
REGISTER
STATUS
LATCH
STATUS
REGISTER
CLK n
GATE n
OUT n
OUT 2
GATE 2
CLK 2
OUT 1
GATE 1
CLK 1
OUT 0
GATE 0
CLK 0
WR
RD
D
7
- D
0
A
0
A
1
CS
OL
M
OL
L
CE
CR
M
CR
L
COUNTER INTERNAL BLOCK DIAGRAM
8
82C54
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