參數(shù)資料
型號: P80CL580
廠商: NXP Semiconductors N.V.
英文描述: Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
中文描述: 低電壓8 - UART的,位微控制器的I2C總線和ADC
文件頁數(shù): 10/80頁
文件大?。?/td> 366K
代理商: P80CL580
1997 Mar 14
10
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I
2
C-bus and ADC
P80CL580; P83CL580
8
FUNCTIONAL DESCRIPTION OVERVIEW
This chapter gives a brief overview of the device.
The detailed functional description is in the following
chapters:
Chapter 9 “Memory organization”
Chapter 10 “I/O facilities”
Chapter 11 “Timers/event counters”
Chapter 12 “Pulse Width Modulated output”
Chapter 13 “Analog-to-digital converter (ADC)”
Chapter 14 “Reduced power modes”
Chapter 15 “I
2
C-bus serial I/O”
Chapter 16 “Standard serial interface SIO0: UART”
Chapter 17 “Interrupt system”
Chapter 18 “Oscillator circuitry”
Chapter 19 “Reset”.
8.1
General
The P8xCL580 is a stand-alone high-performance CMOS
microcontroller designed for use in real-time applications
such as cordless telephone and mobile communications,
instrumentation, industrial control, intelligent computer
peripherals and consumer products.
The device provides hardware features, architectural
enhancements and new instructions to function as a
controller for applications requiring up to 64 kbytes of
Program Memory and/or up to 64 kbytes of Data Memory.
The P8xCL580 contains a 6 kbytes Program Memory
(ROM; P83CL580); a static 256 bytes Data Memory
(RAM); 40 I/O lines; three 16-bit timer/event counters; a
fifteen-source two priority-level, nested interrupt structure
and on-chip oscillator and timing circuit, 4-channel 8-bit
A/D converter, Watchdog Timer and Pulse Width
Modulation output.
The device has two software-selectable modes of reduced
activity for power reduction:
Idle mode
; freezes the CPU while allowing the
derivative functions (timers, serial I/O, ADC, PWM) and
interrupt system to continue functioning.
Power-down mode
; saves the RAM contents but
freezes the oscillator causing all other chip functions to
be inoperative.
In addition, two serial interfaces are provided on-chip:
A standard UART serial interface, and
A standard I
2
C-bus serial interface. The I
2
C-bus serial
interface has byte-oriented master and slave functions
allowing communication with the whole family of I
2
C-bus
compatible devices.
8.2
CPU timing
A machine cycle consists of a sequence of 6 states. Each
state lasts for two oscillator periods, thus a machine cycle
takes 12 oscillator periods or 1
μ
s if the oscillator
frequency (f
osc
) is 12 MHz.
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