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參數(shù)資料
| 型號： | P80C851IBP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS single-chip 8-bit microcontroller with on-chip EEPROM |
| 中文描述： | 8-BIT, 24 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 13/22頁 |
| 文件大?。?/td> | 182K |
| 代理商： | P80C851IBP |
Philips Semiconductors
Product specification
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
1998 Jul 03
13
AC ELECTRICAL CHARACTERISTICS
1, 2
24 MHz Version
24MHz CLOCK
MIN
VARIABLE CLOCK
MIN
3.5
2t
CLCL
–40
t
CLCL
–25
t
CLCL
–25
SYMBOL
1/t
CLCL
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
Data Memory
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWH
t
QVWX
t
WHQX
t
RLAZ
t
WHLH
External Clock
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Erase/write timer constant
3
t
E/W
t
E
t
W
t
S
NE/W
FIGURE
4
4
4
4
4
4
4
4
4
4
4
4
PARAMETER
MAX
MAX
24
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
43
17
17
102
4t
CLCL
–65
17
80
t
CLCL
–25
3t
CLCL
–45
65
3t
CLCL
–60
0
0
17
128
10
t
CLCL
–25
5t
CLCL
–80
10
5
5
5
5
5
5
5
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to RD or WR low
Data setup time before WR
Data valid to WR transition
Data hold after WR
RD low to address float
RD or WR high to ALE high
150
150
6t
CLCL
–100
6t
CLCL
–100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
118
5t
CLCL
–90
0
0
55
183
210
175
2t
CLCL
–28
8t
CLCL
–150
9t
CLCL
–165
3t
CLCL
+50
5, 6
5, 6
6
6
6
5
5, 6
75
92
162
12
17
3t
CLCL
–50
4t
CLCL
–75
7t
CLCL
–130
t
CLCL
–30
t
CLCL
–25
0
67
0
17
t
CLCL
–25
t
CLCL
+25
8
8
8
8
High time
Low time
Rise time
Fall time
17
17
17
17
ns
ns
ns
ns
5
5
20
20
Erase/write cycle time
Erase time
Write time
Data retention time
4
Erase/write cycles
5
4
2
2
10
20
10
10
4
2
2
10
20
10
10
ms
ms
ms
years
cycles
10,000
10,000
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. The power-off fall-time of V
DD
must be less than 1ms to prevent an overwrite pulse from being generated in the EEPROM which can cause
spurious parasitic writing to EEPROM cells. If the V
DD
power-off full-time is greater than 1ms, a power-off reset signal should be generated
to prevent this condition from occurring.
4. Test condition: T
amb
= +55
°
C.
5. Number of erase/write cycles for each EEPROM byte.
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