
Phlips Semiconductors
Product specification
80C652/83C652
CMOS single-chip 8-bit microcontrollers
1997 Dec 05
11
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1. See Figures 9 through 11 for I
DD
test conditions.
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t
r
= t
= 5ns;
V
= V
+ 0.5V; V
= V
–0.5V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = V
DD
. See Figure 9.
3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t
= 5ns; V
IL
= V
SS
+ 0.5V;
V
= V
–0.5V; XTAL2 not connected; Port 0 = P1.6 = P1.7 = V
; EA = RST = V
. See Figure 10.
4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = V
DD
;
EA = RST = V
SS
. See Figure 11.
5. 2V
≤
V
PD
≤
V
DD
max.
6. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I
2
C specification, so an input voltage below 0.3V
DD
will be recognized as a
logic 0 while an input voltage above 0.7V
DD
will be recognized as a logic 1.
7. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V
IN
is approximately 2V.
8. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
OL
s of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
9. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows: Maximum I
OL
= 10mA per port pin; Maximum
I
OL
= 26mA total for Port 0; Maximum I
OL
= 15mA total for Ports 1, 2, and 3; Maximum I
OL
= 71mA total for all output pins. If I
OL
exceeds the
test conditions, V
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
10.Capacitive loading on ports 0 and 2 may cause the V
OH
on ALE and PSEN to momentarily fall below the 0.9V
DD
specification when the
address bits are stabilizing.
DDMAX
for other frequencies can be derived from Figure 1, where FREQ is the external oscillator frequency in MHz. I
DDMAX
is given in mA.
40
30
20
10
0
0
4
8
12
16
(1) MAXIMUM OPERATING MODE: V
DD
= V
DDmax
(2) MAXIMUM IDLE MODE: V
DD
= V
DDmax
These values are valid within the specified
frequency range.
f
XTAL1
(MHz)
I
(mA)
Figure 1. I
DD
vs. Frequency
40
30
20
10
0
0
4
8
12
16
(2)
(1)
24
50
I
(mA)
f
XTAL1
(MHz)
(1) MAXIMUM OPERATING MODE: V
DD
= V
DDmax
(2) MAXIMUM IDLE MODE: V
DD
= V
DDmax
These values are valid within the specified
frequency range.
(1)
(2)