參數(shù)資料
型號(hào)： P80C575EBBB
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 80C51 8-bit microcontroller family 8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
中文描述： 8-BIT, 16 MHz, MICROCONTROLLER, PQFP44
封裝： PLASTIC, SOT-307-2, QFP-44
文件頁數(shù)： 28/40頁
文件大?。?/td> 383K
代理商： P80C575EBBB
Philips Semiconductors
Product specification
80C575/83C575/
87C575
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
1998 May 01
28
AC ELECTRICAL CHARACTERISTICS
T
amb
= 0
°
C to +70
°
C and –40
°
C to +125
°
C, V
CC
= 5V
±
10%, V
SS
= 0V
1, 2
VARIABLE CLOCK
SYMBOL
1/t
CLCL
FIGURE
22
PARAMETER
MIN
MAX
UNIT
Oscillator frequency:
Speed Versions
8XC575
Oscillator fail detect frequency
E
6
16
5.5
MHz
MHz
μ
s
ns
OSCF
0.6
TR
Comparator response time
10
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
Data Memory
22
ALE pulse width
2t
CLCL
–40
t
CLCL
–25
t
CLCL
–25
22
Address valid to ALE low
ns
22
Address hold after ALE low
ns
22
ALE low to valid instruction in
4t
CLCL
–75
ns
22
ALE low to PSEN low
t
CLCL
–25
3t
CLCL
–45
ns
22
PSEN pulse width
ns
22
PSEN low to valid instruction in
3t
CLCL
–70
ns
22
Input instruction hold after PSEN
0
ns
22
Input instruction float after PSEN
t
CLCL
–25
5t
CLCL
–85
10
ns
22
Address to valid instruction in
ns
22
PSEN low to address float
ns
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
WHQX
t
RLAZ
t
WHLH
External Clock
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Shift Register
23, 24
RD pulse width
6t
CLCL
–100
6t
CLCL
–100
ns
23, 24
WR pulse width
ns
23, 24
RD low to valid data in
5t
CLCL
–110
ns
23, 24
Data hold after RD
0
ns
23, 24
Data float after RD
2t
CLCL
–28
8t
CLCL
–150
9t
CLCL
–165
3t
CLCL
+50
ns
23, 24
ALE low to valid data in
ns
23, 24
Address to valid data in
ns
23, 24
ALE low to RD or WR low
3t
CLCL
–50
4t
CLCL
–75
t
CLCL
–30
t
CLCL
–25
ns
23, 24
Address valid to WR low or RD low
ns
23, 24
Data valid to WR transition
ns
23, 24
Data hold after WR
ns
23, 24
RD low to address float
0
ns
23, 24
RD or WR high to ALE high
t
CLCL
–25
t
CLCL
+25
ns
26
High time
12
ns
26
Low time
12
ns
26
Rise time
20
ns
26
Fall time
20
ns
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the 80C32/52 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
25
Serial port clock cycle time
12t
CLCL
10t
CLCL
–133
2t
CLCL
–60
0
ns
25
Output data setup to clock rising edge
ns
25
Output data hold after clock rising edge
ns
25
Input data hold after clock rising edge
ns
25
Clock rising edge to input data valid
10t
CLCL
–133
ns
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