參數(shù)資料
型號： P80C554SBBD
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
中文描述： 8-BIT, 16 MHz, MICROCONTROLLER, PQFP64
封裝： 10 X 10 X 1.40 MM, PLASTIC, LQFP-64
文件頁數(shù)： 31/76頁
文件大?。?/td> 400K
代理商： P80C554SBBD
Philips Semiconductors
Preliminary specification
80C554/83C554/87C554
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I
2
C, PWM,
capture/compare, high I/O, 64L LQFP
2000 Nov 10
31
PCT0
BIT
SYMBOL
FUNCTION
IP1.7
IP1.6
IP1.5
IP1.4
IP1.3
IP1.2
IP1.1
IP1.0
PT2
PCM2
PCM1
PCM0
PCT3
PCT2
PCT1
PCT0
T2 overflow interrupt(s) priority level
T2 comparator 2 interrupt priority level
T2 comparator 1 interrupt priority level
T2 comparator 0 interrupt priority level
T2 capture register 3 interrupt priority level
T2 capture register 2 interrupt priority level
T2 capture register 1 interrupt priority level
T2 capture register 0 interrupt priority level
SU00764
PCT1
PCT2
PCT3
PCM0
PCM1
PCM2
PT2
0
1
2
3
4
5
6
7
(LSB)
(MSB)
IP1 (F8H)
Figure 31. Interrupt Priority Register (IP1)
PCT0H
BIT
SYMBOL
FUNCTION
IP1H.7
IP1H.6
IP1H.5
IP1H.4
IP1H.3
IP1H.2
IP1H.1
IP1H.0
PT2H
PCM2H
PCM1H
PCM0H
PCT3H
PCT2H
PCT1H
PCT0H
T2 overflow interrupt(s) priority level high
T2 comparator 2 interrupt priority level high
T2 comparator 1 interrupt priority level high
T2 comparator 0 interrupt priority level high
T2 capture register 3 interrupt priority level high
T2 capture register 2 interrupt priority level high
T2 capture register 1 interrupt priority level high
T2 capture register 0 interrupt priority level high
SU00984
PCT1H
PCT2H
PCT3H
PCM0H
PCM1H
PCM2H
PT2H
0
1
2
3
4
5
6
7
(LSB)
(MSB)
IP1H (F7H)
Figure 32. Interrupt Priority Register High (IP1H)
Table 3.
Interrupt Priority Structure
SOURCE
NAME
PRIORITY WITHIN LEVEL
External interrupt 0
SIO1 (I
2
C)
ADC completion
Timer 0 overflow
T2 capture 0
T2 compare 0
External interrupt 1
T2 capture 1
T2 compare 1
Timer 1 overflow
T2 capture 2
T2 compare 2
SIO0 (UART)
T2 capture 3
Timer T2 overflow
X0
S1
ADC
T0
CT0
CM0
X1
CT1
CM1
T1
CT2
CM2
S0
CT3
T2
(highest)
↑
↓
(lowest)
Table 4.
Interrupt Vector Addresses
SOURCE
NAME
VECTOR ADDRESS
External interrupt 0
Timer 0 overflow
External interrupt 1
Timer 1 overflow
SIO0 (UART)
SIO1 (I
2
C)
T2 capture 0
T2 capture 1
T2 capture 2
T2 capture 3
ADC completion
T2 compare 0
T2 compare 1
T2 compare 2
T2 overflow
X0
T0
X1
T1
S0
S1
CT0
CT1
CT2
CT3
ADC
CM0
CM1
CM2
T2
0003H
000BH
0013H
001BH
0023H
002BH
0033H
003BH
0043H
004BH
0053H
005BH
0063H
006BH
0073H
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