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參數(shù)資料
| 型號(hào)： | P80C552EHA |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Single-chip 8-bit microcontroller |
| 中文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, SOT-188-2, LCC-68 |
| 文件頁數(shù)： | 13/23頁 |
| 文件大?。?/td> | 185K |
| 代理商： | P80C552EHA |
Philips Semiconductors
Product data
80C552/83C552
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
2002 Sep 03
13
AC ELECTRICAL CHARACTERISTICS
1, 2
16 MHz version
16 MHz CLOCK
MIN
VARIABLE CLOCK
MIN
3.5
2t
CLCL
–40
t
CLCL
–55
t
CLCL
–35
SYMBOL
1/t
CLCL
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
Data Memory
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
DW
t
WHQX
t
RLAZ
t
WHLH
External Clock
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Serial Timing – Shift Register Mode
4
(Test Conditions: T
amb
= 0
°
C to +70
°
C; V
SS
= 0 V; Load Capacitance = 80 pF)
t
XLXL
6
Serial port clock cycle time
t
QVXH
6
Output data setup to clock rising edge
t
XHQX
6
Output data hold after clock rising edge
t
XHDX
6
Input data hold after clock rising edge
t
XHDV
6
Clock rising edge to input data valid
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. t
CLCL
= 1/f
OSC
= one oscillator clock period.
t
CLCL
= 83.3ns at f
OSC
= 12 MHz.
t
CLCL
= 62.5ns at f
OSC
= 16 MHz.
4. These values are characterized but not 100% production tested.
FIGURE
2
2
2
2
2
2
2
2
2
2
2
2
PARAMETER
MAX
MAX
16
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
85
8
28
150
4t
CLCL
–100
23
143
t
CLCL
–40
3t
CLCL
–45
83
3t
CLCL
–105
0
0
38
208
10
t
CLCL
–25
5t
CLCL
–105
10
3
4
3
3
3
3
3
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data before WR
Data hold after WR
RD low to address float
RD or WR high to ALE high
275
275
6t
CLCL
–100
6t
CLCL
–100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
148
5t
CLCL
–165
0
0
55
350
398
238
2t
CLCL
–70
8t
CLCL
–150
9t
CLCL
–165
3t
CLCL
+50
3, 4
3, 4
4
4
4
3
3, 4
138
120
3
288
13
3t
CLCL
–50
4t
CLCL
–130
t
CLCL
–60
7t
CLCL
–150
t
CLCL
–50
0
0
23
103
t
CLCL
–40
t
CLCL
+40
5
5
5
5
High time
4
Low time
4
Rise time
4
Fall time
4
20
20
20
20
ns
ns
ns
ns
20
20
20
20
0.75
492
8
0
12t
CLCL
10t
CLCL
–133
2t
CLCL
–117
0
μ
s
ns
ns
ns
ns
492
10t
CLCL
–133
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