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參數(shù)資料
| 型號： | P80C52X2BN |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 33 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, PLASTIC, MO-015, SOT-129-1, DIP-40 |
| 文件頁數(shù)： | 37/62頁 |
| 文件大?。?/td> | 404K |
| 代理商： | P80C52X2BN |
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Philips Semiconductors
Product data
P80C3xX2; P80C5xX2;
P87C5xX2
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
2002 Jan 24
42
AC ELECTRICAL CHARACTERISTICS (6-CLOCK MODE, 5 V
±10% OPERATION)
Tamb = 0 °C to +70 °C or –40 °C to +85 °C ; VCC = 5 V ±10%, VSS = 0 V1,2,3,4,5
Symbol
Figure
Parameter
Limits
16 MHz Clock
Unit
MIN
MAX
MIN
MAX
1/tCLCL
31
Oscillator frequency
0
30
–
MHz
tLHLL
27
ALE pulse width
tCLCL–8
–
54.5
–
ns
tAVLL
27
Address valid to ALE low
0.5 tCLCL –13
–
18.25
–
ns
tLLAX
27
Address hold after ALE low
0.5 tCLCL –20
–
11.25
–
ns
tLLIV
27
ALE low to valid instruction in
–
2 tCLCL –35
–
90
ns
tLLPL
27
ALE low to PSEN low
0.5 tCLCL –10
–
21.25
–
ns
tPLPH
27
PSEN pulse width
1.5 tCLCL –10
–
83.75
–
ns
tPLIV
27
PSEN low to valid instruction in
–
1.5 tCLCL –35
–
58.75
ns
tPXIX
27
Input instruction hold after PSEN
0
–
0
–
ns
tPXIZ
27
Input instruction float after PSEN
–
0.5 tCLCL –10
–
21.25
ns
tAVIV
27
Address to valid instruction in
–
2.5 tCLCL –35
–
121.25
ns
tPLAZ
27
PSEN low to address float
–
10
–
10
ns
Data Memory
tRLRH
28
RD pulse width
3 tCLCL –20
–
167.5
–
ns
tWLWH
29
WR pulse width
3 tCLCL –20
–
167.5
–
ns
tRLDV
28
RD low to valid data in
–
2.5 tCLCL –35
–
121.25
ns
tRHDX
28
Data hold after RD
0
–
0
–
ns
tRHDZ
28
Data float after RD
–
tCLCL –10
–
52.5
ns
tLLDV
28
ALE low to valid data in
–
4 tCLCL –35
–
215
ns
tAVDV
28
Address to valid data in
–
4.5 tCLCL –35
–
246.25
ns
tLLWL
28, 29
ALE low to RD or WR low
1.5 tCLCL –15
1.5 tCLCL +15
78.75
108.75
ns
tAVWL
28, 29
Address valid to WR low or RD low
2 tCLCL –15
–
110
–
ns
tQVWX
29
Data valid to WR transition
0.5 tCLCL –25
–
6.25
–
ns
tWHQX
29
Data hold after WR
0.5 tCLCL –15
–
16.25
–
ns
tQVWH
29
Data valid to WR high
3.5 tCLCL –5
–
213.75
–
ns
tRLAZ
28
RD low to address float
–
0
–
0
ns
tWHLH
28, 29
RD or WR high to ALE high
0.5 tCLCL –10
0.5 tCLCL +10
21.25
41.25
ns
External Clock
tCHCX
31
High time
0.4 tCLCL
tCLCL – tCLCX
–
ns
tCLCX
31
Low time
0.4 tCLCL
tCLCL – tCHCX
–
ns
tCLCH
31
Rise time
–
5
–
ns
tCHCL
31
Fall time
–
5
–
ns
Shift register
tXLXL
30
Serial port clock cycle time
6 tCLCL
–
375
–
ns
tQVXH
30
Output data setup to clock rising edge
5 tCLCL –25
–
287.5
–
ns
tXHQX
30
Output data hold after clock rising edge
tCLCL –15
–
47.5
–
ns
tXHDX
30
Input data hold after clock rising edge
0
–
0
–
ns
tXHDV
30
Clock rising edge to input data valid
–
5 tCLCL –133
–
179.5
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN=100 pF, load capacitance for all outputs = 80 pF
3. Interfacing the microcontroller to devices with float time up to 45ns is permitted. This limited bus contention will not cause damage to port 0
drivers.
4. Parts are guaranteed by design to operate down to 0 Hz.
5. Data shown in the table are the best mathematical models for the set of measured values obtained in tests. If a particular parameter
calculated at a customer specified frequency has a negative value, it should be considered equal to zero.
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