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參數(shù)資料
| 型號： | P80C52-24 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 22/23頁 |
| 文件大?。?/td> | 319K |
| 代理商： | P80C52-24 |
8XC52/54/58
Table 5. Program Lock Bits and the Features
Program Lock Bits
Protection Type
LB1
LB2
LB3
1
U
U
U
No Program Lock features enabled. (Code verify will still be encrypted by the
Encryption Array if programmed.)
2
P
U
U
MOVC instructions executed from external program memory are disabled from
fetching code bytes from internal memory, EA is sampled and latched on
Reset, and further programming of the EPROM is disabled.
3
P
P
U
Same as 2, also verify is disabled.
4
P
P
P
Same as 3, also external execution is disabled.
NOTE:
Any other combination of the lock bits is not defined.
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(T
A
e
21
§
C to 27
§
C; V
CC
e
5V
g
20%; V
SS
e
0V)
Symbol
Parameter
Min
Max
Units
V
PP
Programming Supply Voltage
12.5
13.0
V
I
PP
Programming Supply Current
75
mA
1/TCLCL
Oscillator Frequency
4
6
MHz
TAVGL
Address Setup to PROG Low
48TCLCL
TGHAX
Address Hold after PROG
48TCLCL
TDVGL
Data Setup to PROG Low
48TCLCL
TGHDX
Data Hold after PROG
48TCLCL
TEHSH
(Enable) High to V
PP
48TCLCL
TSHGL
V
PP
Setup to PROG Low
10
m
s
TGHSL
V
PP
Hold after PROG
10
m
s
TGLGH
PROG Width
90
110
m
s
TAVQV
Address to Data Valid
48TCLCL
TELQV
ENABLE Low to Data Valid
48TCLCL
TEHQZ
Data Float after ENABLE
0
48TCLCL
TGHGL
PROG High to PROG Low
10
m
s
22
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